To appear in Proc. 34th Asilomar Conf. on Signals, Systems, and Computers, Oct. 29 – Nov. 1, 2000. 1 From Basic Concept to Real-Time Implementation: Prototyping WCDMA Downlink Receiver Algorithms – A Case Study M. Guillaud, A. Burg, L. Mailaender, B. Haller, M. Rupp, and E. Beck Lucent Technologies, Wireless Research Laboratory 791 Holmdel-Keyport Road, Holmdel, NJ 07733-0400, USA {maxime,burg,lm,bhaller1,rupp,ericbeck}@lucent.com Abstract In this paper we present an approach to rapid prototyping of advanced signal processing techniques for future wire- less applications currently being adopted within Bell Labs Research. The aim of the “Bell Labs Algorithm Develop- ment and Evaluation” (BLADE) initiative is to devise a de- sign framework specifically targeting the needs (and capa- bilities) of high-level algorithm designers (viz. communica- tion engineers), which enables them to quickly “translate” a research idea into a working real-time system for practi- cal experimentation purposes. The mixed DSP/FPGA im- plementation of a WCDMA testbed is used as an example to describe our initial experience with the proposed design methodology, which is based on a set of commercially avail- able software tools and a platform consisting of off the shelf hardware modules. 1. Introduction Future wireless systems aim to provide higher data rates, improved spectral efficiency and greater capacity. This can be achieved at the cost of increased signal processing com- plexity. The required algorithms are usually derived ana- lytically from mathematical models based on many simpli- fying assumptions [1]. Following this, the original, “opti- mal” procedures nearly always need to be modified (i.e., re- engineered) in order to reduce their computational complex- ity. The performance of the resulting schemes is then typ- ically obtained from computer simulations. Unfortunately, the employed simulation models rarely represent the actual system in sufficient detail, so that the designers are often left with a high degree of uncertainty regarding the real-world behavior of the developed solution. This is especially true when studying multiple antenna systems (such as BLAST [2]) which rely heavily on specific properties of the prop- agation environment. Therefore, researchers in wireless communications are now increasingly confronted with the problem of validating their ideas under realistic conditions and challenged with providing a proof of concept (i.e., they are required to demonstrate that a proposed novel scheme is practically feasible). Consequently, rapid prototyping is becoming essential to evaluate the true performance and ac- curately assess the implementation cost of new signal pro- cessing techniques for wireless applications prior to actual product development in order to minimize the risk of failure [3], [4], [5]. Traditionally, the people involved in generating these new algorithms are communication engineers, who have lit- tle knowledge of real-time system design, i.e., they typically possess limited experience in DSP programming and in writing VHDL code for an FPGA implementation. Our goal was to identify a set of tools and a design flow that would al- low researchers with this type of background to implement their ideas on a flexible real-time prototyping platform. In this paper we present the proposed “Bell Labs Algorithm Development and Evaluation” (BLADE) methodology and describe how it was applied to building a WCDMA testbed, which was selected as an initial test case. 2. The BLADE Approach to Prototyping Most algorithm designers start out by using interactive mathematical software packages such as Matlab, Maple, Mathematica or MathCAD to investigate a novel idea, be- cause these tools provide a wealth of built-in data process- ing and analysis functions as well as extensive graphics capabilities. The next step typically consists of writing a floating-point C program—mainly to speed up the simula- tion runs. In principle, this C code could then be cross- compiled onto a digital signal processor (DSP), but often a single floating-point DSP is unable to meet the stringent real-time constraints imposed by the application. Therefore, it is common practice to employ multiple DSPs and/or map those parts of the system requiring very high speed process- ing onto hardware such as field-programmable gate arrays (FPGAs). These reconfigurable devices are especially well suited for prototyping since they allow to do multiple de- sign iterations quickly. A hardware platform suitable for rapid prototyping of radio systems will therefore consist of