10.1117/2.1201501.005721 On-chip time-of-flight estimation in standard CMOS technology Ion Vornicu, Ricardo Carmona-Gal´ an, and ´ Angel Rodr´ıguez-V´ azquez Single-photon avalanche diodes are integrated with high-speed time-to- digital converters in new cost-effective image sensors. In the last decade, CMOS image sensors (CISs) have reached a considerable level of maturity and their performance is now comparable with CCD sensors, in terms of image quality. CISs have almost completely replaced CCDs in commercial photo cameras and mobile phones. The main advantage of using CMOS technology is the possibility of integrating additional intelligence at the sensor level. Complex image processing algorithms can be run on-chip at high frame rates. A possible future development for CIS technology is to capture 3D information from a scene. This, however, requires active illumination schemes. The most popular approach is to use pulse-modulated illumination, with a jitter in the picosecond range. A properly clocked set of transfer gates is correlated with the received light pulses to derive the time of flight (ToF) and thus the 3D information. The transfer must be carefully designed to provide practical spatial resolution, but this does not work very well, in general, with standard CMOS technology. An alternative is to use single-photon avalanche diodes (SPADs), 1 but this re- quires low defect density, which is rarely achieved with stan- dard CMOS processes. 2 Several techniques can be implemented on-chip, however, to mitigate these effects. Our approach to this problem involves the use of time-gated SPADs, which permits a direct ToF to be determined even with a high dark count rate (DCR) and a low photon detection efficiency (PDE). 3 We have designed an architecture that can perform ToF estimation in standard CMOS technology. Our latest imager, which incorporates this architecture, therefore pushes current technological limits. We fabricated our chip in a 0.18m-1P6M-1.8V (i.e., using one polysilicon and six metal Figure 1. A microphotograph of the 6464-pixel 3D imager. PLL: Phase-locked loop. I/O: Input/output. levels) process and our architecture is based on in-pixel time- to-digital converters (TDCs). Our experimental results indicate that this device is robust and that no pixel-level calibration is required. A microphotograph of our latest chip is shown in Figure 1. A detailed description of this sensor, together with a full character- ization of the TDC array, has previously been reported. 4 We used our own design of a picosecond-incremental-resolution time- interval generator, on field-programmable gate array (FPGA) technology, to make measurements of the chip. 5 The central part Continued on next page