Fabrication and Characterization of Vertically Stacked Gate-AIl-Around Si Nanowire FET Arrays Davide Sacchetio", M. Haykel Ben-Jamaa l , Giovanni De Micheli l and Yusuf Leblebici 2 1 Integrated System Laboratory (LSI), 2Microelectronic System Laboratory (LSM) Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland e-mail: davide.sacchetto@epfl.ch Abstract- We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNW FETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fab- ricated with Cr /NiCr contacts present good subthreshold slope (70mV/dec), IoN/loF F ratio 2:10 4 and reproducible ambipolar behavior. Index Terms-nanowire, FET, multichannel, ambipolar, vertical integration I. INTRODUCTION C ontinuing efforts in Complementary-Metal-Oxide- Semiconductor (CMOS) research have lead to the exponential increase of device integration density during the last 40 years. More recently increasing fabrication costs and increasing overall variability have become an obstacle for the scaling trend. In order to overcome such limitations, considerable research is dedicated for instance to the use of new materials (such as high-x dielectrics with metal gates), dual-gate devices, novel isolation techniques that make use of Silicon-On-Nothing (SON) or Silicon-On-Insulator (Sal) substrates [1]. In particular, dual-gate technology in conjunction with the geometry of the device can enhance the control over the transistor channel. In this sense, further improvements can be achieved with tri-gate, omega-gate or Gate All-Around technologies (GAA) [2]. Recent works explored the vertical stacking of SiNWs as channels for FET devices [3], [4]. The vertically stacked SiNWs represent channels of the same SiNW FET, whose electrostactic control can be enhanched by using a GAA configuration [5]. In addition, SiNW FETs can also be used to build new logic architectures [6], [7] or as ultimate memory architectures for Ultra- Large-Silicon- Integration (ULSI) [8], [9]. In this work we discuss novel and promising fabrication method for vertically-stacked SiNW FETs with different num- ber of channels on bulk Si wafers. The reported method has also been applied to fabricate single channel devices that demonstrate excellent reproducible performance. II. RELATED WORK Recently, a multichannel structure with GAA configuration has been proposed as a candidate for high-performance devices. Its implementation has the advantage of enhanced on-current (ION) along with low leakage as well as a small footprint for multi-finger (multi-channel) devices [10], [4]. The fabrication process described in [10], [4] is based on creating epitaxial layers to alternate Si and SiGe layers one on top of each other. A vertical trench is etched in the grown structure. A successive 978-1-4244-4353-6/09/$25.00 ©2009 IEEE SiGe selective etching leaves vertically-stacked Si nanowires. Hydrogen annealing is then used to change the SiNW shapes from rectangular to circular, thus yielding channels with less surface roughness and improved controllability. An alternative approach for the fabrication of vertically- stacked SiNWs [11] is based on producing a scalloped trench in bulk silicon by means of Deep Reactive Ion Etching (DRIE). Sacrificial oxidation steps are performed to reduce the dimen- sions of the trench. Thanks to scalloping, the Si trench is totally consumed in its thinner parts, leaving a vertical stack of suspended SiNWs. Although the DRIE process defines trenches of micrometer dimensions, the iteration of oxidation steps is capable for reducing the structures to suspended nanowires with of 20 nm in diameter [11]. This approach has also been demonstrated to be suitable for producing vertically stacked SiNW with small dimensions and different section shapes [12], yet it has not been used so far for GAA FET fabrication. III. DEVICE FABRICATION In our work we produce vertical SiNW arrays by means of optical lithography with 1 Mm resolution limit. Sub-micrometer features are obtained through sacrificial oxidation steps. Al- though the integration density would have been further in- creased by means of advanced lithography, the developed pro- cess already allows us to produce very high channel densities without making use of non standard fabrication steps. We start by defining a photoresist line on a p-type (N rv 10 15 ) silicon bulk wafer (see Fig. 1.a). Then a DRIE technique (also called Bosch process) is performed. This technique, that alternates a plasma etching with a passivation step, has been optimized to produce a scalloped trench in silicon with high reproducibility. Etching time, passivation time and plasma platen power have been optimized in order to enhance the scalloping effect. The application of the DRIE technique gives a trench like the one depicted in Fig. 1.b. The flexibility of the process allows us to change the number of scallops easily. After a wet oxidation step (see Fig. 1.c) vertically stacked SiNWs are formed. Then the cavities produced by the Bosch process are filled with photoresist. After a combination of chemical mechanical polishing (CMP) and BHF dip, the wet oxide is re- moved around the NWs (see Fig. 1.f). The oxide at the bottom of the cavity is left to isolate the substrate from the successive processes. The vertical structure obtained is then oxidized to produce a high quality dry oxide (20 nm thick, see Fig. 1.g) as gate dielectric. Then between 200 nm and 500 nm of Low Pressure Chemical Vapour Deposition (LPCVD) polysilicon is deposited (Fig. 1.h). The polysilicon gate is patterned by means of a combination of isotropic and anisotropic recipes (see Fig. 1.i). A final field oxide isolation and Al or Cr /NiCr patterning make the external electrical connections.