Effects of the growth rate on the quality of 4H silicon carbide films for MOSFET applications M. Camarda 1) , S. Privitera 1) , R. Anzalone 1) , N. Piluso 1) , P. Fiorenza 1) , A. Alberti 1) , G. Pellegrino 1) , A. La Magna 1) , F. La Via 1) C. Vecchio 2) , M. Mauceri 2) , G. Litrico 2) , A. Pecora 2) , D. Crippa 3) 1) IMM-CNR, Z.I. VIII Strada, 5, 95121, Catania, Italy 2) Epitaxial Technology Center, XVI Strada, Pantano d'Arci, 95121 Catania, Italy 3) LPE spa, Via falzarego 8. 20021 Baranzate, Italy E-mail: massimo.camarda@imm.cnr.com Keywords: surface morphology, growth rate, density of interface state traps. Abstract In this paper we investigate the role of the growth rate (varied by changing the Si/H 2 ratio and using TCS to avoid Si droplet formation) on the surface roughness (R q ), the density of single Shockley stacking faults (SSSF) and 3C-inclusions (i.e. epi-stacking faults, ESF). We find that optimized processes with higher growth rates allow to improve the films in all the considered aspects. This result, together with the reduced cost of growth processes, indicates that high growth rates should always be used to improve the overall quality of 4H-SiC homoepitaxial growths. Furthermore we analyze the connection between surface morphology and density of traps (D it ) at the SiO 2 /SiC interface in fabricated MOS devices finding consistent indications that higher surface roughness (‘step-bunched’ surfaces) can improve the quality of the interface by reducing the D it value. Introduction 4H-Silicon Carbide is one of the most mature post-Si material in the field of high voltage/high power devices with demonstrated power DMOSFET, implanted VJFETs, PiN diodes and Schottky diodes [1]. High quality 4H-SiC films are mostly grown on (0001) surfaces slightly misoriented (2°-8°) towards the <11-20> direction to avoid polytype inclusions (mainly 3C, named epi-stacking faults, ESF). This growth method, named "step-controlled epitaxy", is known to generate different types of surface instabilities (nano-faceting, step bunching and step meandering) [2,3,4] which, depending on the specific fabricated device and characteristics of the surface morphology, can cause electric field crowding (resulting in the increase the leakage current of Schottky diodes [5,6] or alter the oxide breakdown characteristics in metal-oxide-semiconductor field effect transistors MOSFETs [7]. It is thus mandatory to control the surface morphology of the films during all process steps for high quality, reliable, device characteristics. It has been found that these instabilities are the result of a competition between two opposing tendencies [3]: the former is energetic (step-step attractive strain interaction, step reactivity and step-surface dangling bond densities) which favours the re-organization in terms of nano-ondulations, the latter is kinetic which, by increasing the overall randomness of the deposition, hinders ordered configurations. Aiming to further elucidate the energetic/kinetic competition and to directly explore the impact of surface morphology on the density of defects at the SiC/SiO 2 interface (which, in turn, will impact channel characteristics in MOSFETs [8]) we have analyzed three ~8 µm thick 4H-SiC films with a n-type doping of 10 16 cm -3 grown on 4° <11-20> substrates setting the growth rate (by altering the Si/H 2 ratio) at 4 µm/h (sample a), 27 µm/h (sample b) and 60 µm/h (sample c). In order to modify the surface roughness a high temperature annealing at 1650°C, low pressure (20 millibar) in Argon gas was performed on (b) sample for 30’. Materials Science Forum Vols. 778-780 (2014) pp 95-98 Online available since 2014/Feb/26 at www.scientific.net © (2014) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.778-780.95 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, www.ttp.net. (ID: 192.167.161.20, Istituto per la Microelettronica e Microsistemi IMM-CNR, Catania, Italy-19/03/14,11:45:18)