Published in IET Computers & Digital Techniques Received on 1st July 2008 Revised on 1st June 2009 doi: 10.1049/iet-cdt.2008.0071 In Special Issue on Networks on Chip ISSN 1751-8601 Processing while routing: a network-on-chip- based parallel system S.R. Fernandes 1 B.C. Oliveira 2 M. Costa 2 I.S. Silva 2 1 Department of Exact Science and Natural, Rural Federal University of the Semi-Arid, BR 110, Km 47, Bairro Presidente Costa e Silva, CEP 59.625-900 Mossoro ´, RN, Brazil 2 Department of Informatics and Applied Mathematics, Federal University of Rio Grande do Norte, PO Box 1524, Campus Universita ´rio Lagoa Nova CEP 59072-970 Natal, RN, Brazil E-mail: silvio@ufersa.edu.br Abstract: Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, since it is impossible to use bus-based solutions. Other interconnection solutions have been employed. However, they are area and power expensive. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilisation of network-on-chip not only as interconnection but also as the processing datapath. 1 Introduction Nowadays, multi-core processors, dual-, quad- and eighth core are a market reality and probably, in the next generation of computing system, we will see many-core architectures [1]. It will be possible not only because we are actually in the billion transistors era but also because we have been pushed up by design of on-chip interconnection networks. Bus-based design remains useful while the number of cores in the processor is kept to a limit. However, with the continuous growth of integration capability this will not hold for a long time. On the other hand, more powerful interconnections, such as network-on-chip (NoC), are largely studied in a number of scientific papers. This communication architecture comes at the price for more area overhead because of the routers needed for messages sending. In this reality, the NoC becomes the interconnection network that, at the same time, symbolises a solution and a problem. As a solution, NoC approach to system design answer with scalability, parallel communication, reusable structure and point-to-point interconnection. As a problem, NoC requires more chip area and more power. The most traditional NoC architecture consists of a set of directed connected routers with a local port dedicated to the source and destinations for messages flows. In this design and in interconnection networks, in general, the routers are responsible only for the data transmission. This paper proposes original NoC-based system architecture and a computational model, the IPNoSys system, where the routers are also responsible for the execution of operations, besides the routing process. The following section presents the related works including the concepts of NoC and queue machines, which are technical premises to IPNoSys. Section 3 presents the IPNoSys architecture and its main concepts. Section 4 presents the simulation scenarios and results as well as a comparison between IPNoSys and a cycle accurate virtual platform. Section 5 presents the conclusions and future works. 2 Related works In the literature it is possible to find lots of papers concerning the design of NoC and bringing a number of technical contributions. However, such contributions are related only to interconnection mechanisms, none of them are able to incorporate the execution of application instruction as the IET Comput. Digit. Tech., 2009, Vol. 3, Iss. 5, pp. 525–538 525 doi: 10.1049/iet-cdt.2008.0071 & The Institution of Engineering and Technology 2009 www.ietdl.org