Advances in 3D CMOS Sequential Integration P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali, C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, O. Thomas, O. Cueto, N. Bouzaida, D.Fleury 2 , A. Amara 1 , S. Deleonibus and O. Faynot. CEA, LETI, MINATEC, 17 rue des Martyrs F38054 Grenoble, France 1 ISEP, 21 rue d’Assas, 75270 Paris cedex 06 France 2 STMicroelectronics, 850 rue Jean Monnet F38926 Crolles, France Tel: 33 438782329, Fax: 33 438783034, e-mail: perrine.batude@cea.fr Abstract For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4Å of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization. Introduction 3D integration generates great interest to solve the fundamental limits of scaling e.g. increasing delay in interconnections [1], development costs and variability [2]. 3D sequential integration, by opposition to parallel (or back-end or TSV 3D integration) is the only technological option enabling to fully benefit from the third dimension potential at the transistor scale thanks to its high alignment precision (σ SEQ ~10nm[3] compared to σ TSV ~0.5µm [4]). The sequential processing of bottom and top FET is however challenging because of the potential detrimental impact on bottom FET of the top FET processing. In this paper, we demonstrate the possibility of obtaining regular 2D performances within a 3D sequential integration scheme. We further investigate the unique features of low temperature process. Finally, we quantify for the first time, the electrostatic coupling between the layers. Device fabrication P and N FDSOI transistors with 5mn HfO 2 and TiN/Poly-Si N + doped gate stack were fabricated on the bottom layer (fig.1). Thin Inter Layer Dielectric (ILD) was deposited and planarized on top of these transistors. A low temperature (200°C) molecular bonding of SOI substrates was used to obtain perfect quality top active layers. Depending on pre-bonding planarization, thin Inter-Layer Dielectric (ILD) of 110 nm (fig.2) and ultra Thin ILD (UTILD) of 60nm have been obtained. Top MOSFETs have been then processed with an overall thermal budget limited to 600°C. Solid Phase Epitaxy (SPE) at 600°C has been used for dopant activation. Results and discussion Reaching individual 2D transistor performances To be a serious alternative to regular 2D transistors, 3D sequential integration has to demonstrate its ability to integrate the same performance boosters. Use of low temperature molecular bonding to realize top active layers is a remarkable way to fit with this requirement. It indeed allows classical bottom layer salicidation which has not yet been achieved with recristallization or growth techniques due to intrinsic technological challenges [5-7]. Fig.1: Description of the process flow Thanks to Fluorine implantation into NiSi, we manage to design a morphologically robust salicide (fig.3-a). Fig.4 shows the beneficial impact of F on the sheet resistance of blanket wafers as a function of annealing time @ 600°C. After a complete top integration (thermal budget is summarized fig.3-b) R sheet of NiSi(F) is still around its original value (12 to 14Ω/sq) which is just above the standard NiSi R sheet used for the top FET, fig.5. A second unique advantage of bonding is that it allows independent optimization of the stacked layers: channel material [7, 8] and/or crystalline orientation of top and bottom FETs. For the first time we were able to process independently (110) PFETs on top of (100) NFETs. Fig.6 shows the measured mobility of (110) PFETs in the <100> direction. Best mobility values are BOX 1/ Optimized FDSOI bottom MOS  Classical FDSOI process (high TB) with Hf0 2 /TiN stack  Optimized Ni Salicidation F implantation in NiSi 2/ High quality top film  Suppression of MOS topography by CMP  Low temperature bonding of SOI (110 and 100 surface orientation)  Initial substrate removal BOX ILD 3/ Low temperature FDSOI MOSFET  FDSOI MOS (TB<650°C) with Hf0 2 /TiN stack  Low T dopant activation (SPE)  Low T epitaxy (SiGe 30%) BOX 4/ Multilayer contact process  3D dense contact realization  Single step lithography BOX 97-4244-5640-6/09/$26.00 ©2009 IEEE IEDM09-345 14.1.1