IOP PUBLISHING SEMICONDUCTOR SCIENCE AND TECHNOLOGY Semicond. Sci. Technol. 24 (2009) 115008 (6pp) doi:10.1088/0268-1242/24/11/115008 Theoretical analysis of the RESET operation in phase-change memories S Braga, A Cabrini and G Torelli Department of Electronics, University of Pavia, Via Ferrata 1, 27100, Pavia, Italy E-mail: alessandro.cabrini@unipv.it Received 23 March 2009, in final form 4 August 2009 Published 9 October 2009 Online at stacks.iop.org/SST/24/115008 Abstract Phase-change memories (PCMs) are promising candidates for multilevel non-volatile storage, which is allowed by the wide programming window. The multilevel approach requires good control of the programmed cell resistance. For any multilevel programming strategy, the RESET operation plays a key role for the accuracy of the intermediate programmed resistance levels. In this paper, we analyze the impact of the applied RESET pulse amplitude and the fabrication process spreads on the RESET resistance distribution. To this end, we developed a model to estimate the impact of device parameter spreads on the amorphous cap thickness and, hence, on the cell resistance obtained after a RESET operation. The proposed model is verified by means of experimental characterization on a PCM-cell array. (Some figures in this article are in colour only in the electronic version) 1. Introduction Phase-change memories (PCMs) have recently gained much attention among emerging semiconductor non-volatile storage technologies. A PCM cell is based on a thin layer of chalcogenide alloy (Ge 2 Sb 2 Te 5 , GST), which can be reversibly switched between two structural phases having significantly different electrical resistivity: the amorphous phase (highly resistive) and the (poly)crystalline phase (less resistive). Phase transition is achieved via thermal stimulation induced by means of Joule heating: the temperature inside the material is indirectly controlled by applying a suitable electrical pulse to the cell. In bi-level applications, a PCM cell is programmed either to the full-SET state (minimum resistance) or to the full-RESET state (maximum resistance). The possibility of multi-level (ML) storage (i.e., the possibility of storing more than one bit per cell) is allowed by the large difference between the resistances of the RESET and the SET state. The ML approach in PCM devices [1, 4] requires accurate programming of the cell resistance to predetermined intermediate levels. Two alternative ML programming strategies have been proposed in the literature, namely, partial-SET and partial-RESET programming. In the former case, the PCM cell is first programmed to the full- RESET state and, then, partial-SET pulses are applied in order to partially crystallize the amorphous volume [4]. In the latter case, the PCM cell is first programmed to the full- SET state and, then, the GST material is partially amorphized by means of partial-RESET pulses [5]. In both cases, the resistance of the intermediate programmed states depends on the distribution of the amorphous and crystalline phases inside the GST layer. In particular, the thickness of the amorphous cap obtained after the partial-RESET operation is a key parameter to control the resistance of the intermediate states in the case of partial-RESET programming. However, the amorphous cap thickness is also important in partial-SET programming since, in this case, it affects the maximum value of the cell resistance and, hence, the width of the programming window (i.e., the resistance range where all programmed states must be allocated). The amorphous cap thickness and, as a consequence, the cell resistance are highly sensitive to the process spreads of device parameters (e.g. heater, select and bias transistors). Optimized geometries have been proposed in the literature [6–9] in order to limit the sensitivity of the programmed resistance values to fabrication process spreads while Ozatay et al suggest that using sharp edges in the cell geometry (e.g. rectangular contacts) can facilitate multilevel operation [2]. Nonetheless, when using irregular shapes, the sensitivity to fabrication spreads is expected to be higher with respect to the case when regular structures are used. In this respect, it is worth noting that a higher spread leads to a lower 0268-1242/09/115008+06$30.00 1 © 2009 IOP Publishing Ltd Printed in the UK