A Comprehensive DC/AC Model for Ultra-Fast NBTI in Deep EOT Scaled HKMG p-MOSFETs N. Goel 1 , S. Mukhopadhyay 1 , N. Nanaware 1 , S. De 2 , R. K. Pandey 2 , K. V. R. M. Murali 2 and S. Mahapatra 1 ** 1 Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India 2 SRDC, IBM Bangalore 560045, India (**Phone: +91-222-572-0408, Fax: +91-222-572-3707, Email: souvik@ee.iitb.ac.in) Abstract— DC and AC NBTI in deep EOT scaled HKMG p- MOSFETs with different IL (scaled to sub 2Å) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔV IT-IL ) at Si/IL interface, hole trapping (ΔV HT ) in IL bulk and trap generation (ΔV IT-HK ) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict V T shift (ΔV T ) during and after DC stress, dependence on pulse duty cycle (PDC) and frequency (f) for AC stress, and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied, and end-of-life degradation has been estimated. Keywords- NBTI, HKMG, Ultrafast-MSM, interface trap generation, Reaction-Diffusion model, hole trapping, Oxygen vacancy, DCIV measurement, Flicker noise measurement, DFT simulation. I. INTRODUCTION Negative Bias Temperature Instability (NBTI) is a serious reliability issue for SiON and HKMG p-MOSFETs [1], [2]. It results in temporal shift in device parameters like threshold voltage (ΔV T ), transconductance (Δg m ), linear and saturation drain current (ΔI DLIN , ΔI DSAT ), drain-gate capacitance (ΔC GD ) etc [3]. NBTI recovery is a well-known phenomenon, which results in several challenges for proper characterization and modeling [4]. Recovery of NBTI reduces V T shift (ΔV T ) and other parameters for AC compared to DC stress [5], [6] and hence is beneficial for switching logic circuits [7]. Note that most recent NBTI studies on HKMG devices having scaled EOT have been done using slower measurement methods [2], [8], [9]. Since NBTI recovers after stress, Ultra-Fast Method (UFM, ~μs delay) is necessary to obtain recovery artifact free data. Ultrafast On-The-Fly (UF-OTF) is such a method that doesn’t suffer from recovery artifacts [10], although it needs mobility correction for correct estimation of ΔV T [11]. It also cannot measure ΔV T recovery at low gate bias (V G,REC ) at or close to 0V. To overcome these limitations, Agilent B1530 based Ultra-Fast Measure-Stress-Measure (UF-MSM, ~10μs delay) technique has been developed and recently used for measuring DC and AC NBTI in HKMG p-MOSFETs [12], [13], which is also used in this work. Note, it is important to measure ΔV T during DC and AC NBTI stress with identical measurement delay, to obtain correct AC/DC ratio for AC pulses having different f and PDC values. As recently reviewed [4], NBTI physical mechanism has been a subject of much debate. In spite of irrefutable proof of trap generation and recovery during and after NBTI stress in SiON and HKMG p-MOSFETs [1], [4], [9], [13]-[20], some authors proposed trapping-only models for predicting DC and AC NBTI [21]-[23], which has no physical justification. The model proposing strong correlation between generation of new traps and trapping [24] has been shown to be incapable of predicting experimental data. Although a modified version of [24] has been proposed [25], it has many independently adjustable parameters, and no evidence has been shown that the new model can predict ultra-fast DC and AC NBTI under different experimental conditions, and for SiON and HKMG devices with different gate insulator processes. On the other hand, a recent framework invoked uncorrelated interface trap generation (ΔV IT ) and hole trapping (ΔV HT ) contributions to predict DC and AC NBTI and their gate insulator process dependence in both SiON and HKMG p-MOSFETs [4], [13]. In this paper, the framework proposed in [4], [13] is used to predict UF-MSM ΔV T data obtained for DC and AC NBTI experiments in scaled EOT HKMG devices. The model uses correlated interface trap generation at Si/IL interface (ΔV IT-IL ) and at IL/HK interfacial transition layer (ΔV IT-HK ), together with uncorrelated hole trapping in process related traps in IL bulk (ΔV HT ) and can predict experimental data for different conditions for DC and AC stress, such as: (a) DC stress at various stress gate bias (V G,STR ) and Temperature (T); (b) DC recovery after stress at different V G,STR and stress time (t STR ), recovery at different T and recovery bias (V G,REC ); (c) PDC dependence of AC stress at different f and pulse low bias (V G,LOW ); (d) f dependence (in Mode-A) and f independence (in Mode-B) for AC stress at different PDC and V G,LOW ; and (e) Gate insulator process dependence. Density Functional Theory (DFT) simulations are used to identify the precursor of interface trap generation at the IL/HK transition layer as Hydrogen passivated Oxygen vacancy defects (Ov-H). Trap generation is calculated using the double interface Reaction- Diffusion (RD) model [4], hole trapping using an analytic model, and the occupancy of generated traps also using an analytic model [13]. The model can also predict DC and AC NBTI data at long stress time and reliably estimate end-of-life degradation for HKMG devices having different EOT. II. DEVICE AND MEASUREMENT DETAILS HKMG p-MOSFETs used in this work have been made using gate first integration, have dual layer RTP-IL/ALD-HK 978-1-4799-3317-4/14/$31.00 ©2014 IEEE 6A.4.1