1 Practical Performance and Credit Assignment Efficiency of Analog Multi-layer Perceptron Perturbation Based Training Algorithms Marwan A. Jabri Systems Engineering and Design Automation Laboratory Sydney University Electrical Engineering NSW 2006 Australia marwan@sedal.su.oz.au SEDAL Technical Report 1-7-94 Abstract Many algorithms have been recently reported for the training of analog multi-layer perceptron. Most of these algorithms were evaluated either from a computational or simulation view point. This paper applies several of these algorithms to the training of an analog multi-layer perceptron chip. The advantages and shortcomings of these algorithms in terms of training and generalisation performance and their capabilities in a limited precision environment are discussed. Extensive experiments demonstrate that a trade-off exists between the parallelisation of perturbations and the efficiency of credit assignment. Two semi-parallelisation heuristics are presented and are shown to provide advantages in terms of efficient exploration of the solution space and fewer credit assignment confusions. 1 INTRODUCTION Analog microelectronic implementations of the multi-layer perceptron (MLP) offer a number of attractive aspects: they provide an inherent parallelism since computational elements can be highly compact; in many real-world applications they do not require expensive and bulky analog to digital converters; when implemented using sub-threshold design techniques, the resulting system can oper- ate at very low power; analog implementations can also provide higher operating speeds than digital implementations within their precision and noise margins. The attractive aspects of analog computation come with a list of “obstacles”. Resolution is limited in practice to less than 8 bits which can degrade the performance of learning algorithms. Noise immu-