Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams Raimund Ubar, Stephen Adeboye Oyeniran Tallinn University of Technology Computer Engineering Department Estonia Mario Schölzel 1 , Heinrich T. Vierhaus 2 1 University of Potsdam, 2 Technical University of Brandenburg, Germany Abstract—A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend step by step the fault- free core of the system by exploiting the knowledge about already successfully tested parts of the system. In case when the proof fails, fault diagnosis will follow. To cope with the complexity of multiple fault masking mechanisms, high-level decision diagrams (HLDD) are used. The proposed method can be regarded as a generalization of the logic level test pair approach for identifying fault-free wires in gate-level networks. Preliminary experimental results, and a discussion of the complexity of the method is presented. Keywords—digital systems, multiple faults, fault masking, high- level decision diagrams I. INTRODUCTION The technology advancements impose new challenges to testing systems-on-chip as device geometries shrink and the complexity of SOCs increase. Traditional test approaches are based on a single fault assumption, but assuming only single fault cases cannot be any more valid for today’s nanoscale circuits, because the effect of fault masking due to multiple faults remains in this case neglected. A complete test for single faults, in general, may be either incomplete for detecting multiple faults due to possible fault masking, or may result in wrong fault diagnosis. Some results have been achieved in test generation for multiple stuck-at-faults (SAF) at gate-level [1-6]. The main idea of these methods has been to use test pairs to identify fault-free lines in circuits, instead of finding separate test patterns for detecting each SAF separately. The advantage of these methods is that there is no need for creating of single or multiple fault lists, but the complexity of test generation is still close to that of single SAF test generation. The method [2] is based on 16-valued simulation, whereas in [5] an ATPG algorithm based on 7-valued calculus was developed. In [6], a method was proposed based on test pair analysis of the given test, and constructing additional pairs for undetected faults. The paper [4] presents a two phase method where first, the test pairs are found to detect the target SAF independently of other faults, and thereafter, a sophisticated branch and bound procedure is used to complete the test set generation for the faults undetected during the first phase. In [7, 8] it was shown that test pairs not always can avoid fault masking. In [9, 10], a generalization of the test pair conception was proposed by introducing a new test structure as a test group. The necessary and sufficient conditions were formulated for test groups capable to detect any non-redundant multiple fault in a combinational circuit. The meaning of a test group is to identify a fault-free sub-circuit instead of proving the correctness of a single wire only as in case of test pairs. The conception of test groups was developed using topological analysis of paths in Structurally Synthesized BDDs (SSBDD) [11-13]. In this paper we generalize the logic level test group approach for identifying fault-free sub-circuits in digital systems (systems-on-chip) represented at higher register- transfer levels (RTL) or functional levels using High-Level Decision Diagrams (HLDD). The faults of any multiplicity are assumed to be present in the system, and there will be no need to enumerate the faults. The goal of using test groups is to extend step by step the fault-free core of the system by exploiting the knowledge about already successfully tested parts of the system. In case when the test group will fail, fault diagnosis will follow in the part of the system targeted by failing test group. The rest of the paper is organized as follows. Section 2 introduces the concept of topological view on testing of logic level circuits with SSBDDs and explains the meaning of test groups. Section 3 presents the method of modeling digital systems with HLDDs on the example of a VLIW processor, and introduces two classes of high-level faults. In Section 4 we develop a new method of test generation using high-level test groups for testing multiple faults. In Section 5 we give estimations for test length produced by the new method, and compare it with a straightforward method. Section 5 concludes the paper. II. TOPOLOGICAL VIEW ON THE PROBLEM OF FAULT MASKING IN LOGIC LEVEL CIRCUITS In the following we give a short explanation on the method [10] of proving the correctness of a gate-level sub-circuit (core) 978-1-4673-9994-4/15$31.00 ､2015 IEEE 2015 10th International Design & Test Symposium (IDT) 66