T h e I E E E I n t e rn a t i o n a l S y mp o s i u m o n D e f e c t a n d Fa u l t T o l e ra n c e i n V L S I S y s t e ms – “ D FT ’ 0 2 ” , Vancouver, BC, Canada, 6-8 November 2002 390 CMOS Standard Cells Characterization for I DDQ Testing Witold A. Pleskacz, Tomasz Borejko and Wieslaw Kuzmicz Institute of Microelectronics & Optoelectronics Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, POLAND e-mail: pleskacz@imio.pw.edu.pl Abstract This paper describes the CMOS standard cells characterization methodology for I DDQ testing. Defect statistics was taken into account and critical area approach was used to generate compact test sets. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. Experimental results for gates from industrial standard cell library were presented. The complete bridging fault set and different types of the simulation conditions of shorts at inputs of logic gates (“Wired-AND” and “Wired-OR” conditions) were considered. 1. Introduction I DDQ testing has been established as an effective and increasingly popular method of detecting realistic faults in CMOS circuits [1-8]. In this method quiescent power supply current (I DDQ ) of the IC under test is monitored and compared to the predefined reference current. This relies on the fact that transistors of a CMOS circuit pass current through only during state changes and do not pass in quiescent state (except leakage current). In a faulty chip the quiescent current is a few orders of magnitude larger than the I DDQ in a defect-free circuit. I DDQ testing procedure applies a set of test vectors, allows circuit to settle to a quiescent state, and then measures I DDQ . A fault will be detected if the measured I DDQ is larger than the reference current. One of the challenges with voltage test generation is to achieve good controllability and observability of the circuit under test to obtain high fault coverage. In contrast [9,10], I DDQ testing has very good observability because it automatically propagates fault effect through the power supply line. This feature greatly simplifies test vector generation. There are many previous works on test pattern generation for I DDQ testing, e.g. [11-14], but very limited work has been reported in literature about layout-driven test generation [15] methods for current testing. Such a method was used in [16] for comparison of the performance of two test generation techniques, stuck-at fault testing and current testing, when applied to CMOS bridging faults. However, defect statistics were not taken into account. Inductive fault analysis [17,18] was used in [19] to reduce the fault set size, but defect occurrence probabilities were not available at the time of test patterns generation. In [20] Monte Carlo- based inductive contamination analysis was demonstrated for complete fault characterization of standard cell libraries. Such a characterization can be applied for very accurate assessment of defect coverage and test generation. Nevertheless this method is too complex and time consuming to be used for test generation purposes. In this paper critical area approach based on a commercial CAD tool (Dracula) was used for estimation of probabilities of occurrence of physical defects. Functionality of analyzed gates from a standard cell library was verified by using transistor-level simulation. The complete bridging fault set (including multiple shorts) was considered. The proposed characterization methodology takes into account the physical design of the characterized cell and therefore it allows to find the types of faults which may occur in a real IC, determine their probabilities, and generate compact test sets which detect these faults. This characterization process may be computationally expensive, but it should be done only