Modeling and Design of Asynchronous Circuits MARK B. JOSEPHS, STEVEN M. NOWICK, AND C. H. (KEES) VAN BERKEL, MEMBER, IEEE This technology review explores the behavioral and structural design domains for asynchronous circuits and systems. It proceeds bottom up, introducing relevant concepts, terminology, and tech- niques through a succession of simple examples. There are seven main points. 1) Signal transitions provide a key to understanding the switch- ing behavior of asynchronous logic. 2) Burst-mode circuits and speed-independent control circuits offer reliable operation that is free from glitches. 3) Various notations are available for specification of control circuitry and as a starting point for logic synthesis. 4) Bundled data and delay-insensitive coding schemes are suit- able for representing data because they address the issues of data validity and completion detection. 5) Asynchronous networks, constructed from modules and channels, provide a systems architecture for asynchronous design. 6) Handshaking on channels, which controls data communica- tion and synchronization between modules, is implemented using signal transitions. 7) The translation of algorithmic descriptions into asynchronous networks facilitates an automated approach to large-scale system design. Keywords— Asynchronous circuits, bundled data, burst-mode circuits, delay-insensitive codes, handshaking, hazards, self-timed circuits, signal transitions, speed-independent circuits, State Graphs. I. INTRODUCTION We are concerned with the behavior and structure of digital systems, whether of microprocessors, digital signal- processor (DSP) cores, application-specific integrated cir- cuits (ASIC’s), or individual submodules. The transfer of data between registers in such systems needs to be regulated so as to ensure that data are current and valid whenever they are processed. The standard approach is to synchronize the entire system to a common periodic signal (the clock). Manuscript received September 21, 1998. This work was supported by the European Commission under Working Group 21949 ACiD-WG as part of the ESPRIT Fourth Framework and by the National Science Foundation under Grants MIP-9501880 and CCR-97-31803. M. B. Josephs is with the Center for Concurrent Systems and VLSI, School of CISM, South Bank University, London SE1 0AA U.K. S. M. Nowick is with the Department of Computer Science, Columbia University, New York, NY 10027 USA. C. H. van Berkel is with Philips Research Laboratories, Eindhoven 5656 AA The Netherlands, and with Eindhoven University of Technology, Eindhoven 5600 MB The Netherlands. Publisher Item Identifier S 0018-9219(99)00879-8. Asynchronous, or self-timed, design contrasts with this approach in that the task of regulation is devolved to local control signals [11], [40]. In the same way that the rising and falling edges of a clock start or stop the flow of data through latches in a synchronous circuit, the transitions (not simply the levels) of local control signals regulate activity in an asynchronous circuit. In Section II, we shall look at the behavior of logic gates, in terms of how they propagate signal transitions. State Graphs will be introduced as a convenient notation for modeling this switching behavior. Complex control functions can be realized by combining gates into burst-mode circuits or speed-independent (SI) circuits (Section III). These two classes of circuits differ in how their correct operation depends upon the relative delays along different signal paths. When designing control circuitry, one begins by writing a specification. A variety of notations have been devised for that purpose and a selection of these will be illustrated in Section IV. Synthesis takes us from specification down to logic implementation. In Section IV, we shall also consider some of the automated computer-aided design (CAD) tools currently available. Data processing is our concern in Section V. The problem here is to determine when the processing task has com- pleted. We introduce and contrast the two approaches of data-bundling and delay-insensitive coding. At a higher level of abstraction, asynchronous systems can be constructed out of modules (engaging in control and data-processing functions) and channels. Handshaking as the means of communication and synchronization be- tween modules is central to this systems architecture, as is discussed in Section VI. Moreover, high-level algorith- mic descriptions can be automatically translated into such asynchronous networks. II. SWITCHING BEHAVIOR OF LOGIC GATES Digital logic design is concerned with the processing of signals with discrete values, the logic levels zero and one. The basic processing element is the logic gate, which computes an output signal as a function of input signals. For example, the function computed by an OR gate with two inputs, named and , and an output, named , is 0018–9219/99$10.00  1999 IEEE 234 PROCEEDINGS OF THE IEEE, VOL. 87, NO. 2, FEBRUARY 1999