Unifying approach for Jitter Transfer Analysis of Bang-Bang CDR Circuits Ahmed Gabr Department of Electronics Carleton University Ottawa, Canada agabr@doe.carleton.ca Tad Kwasniewski Department of Electronics Carleton University Ottawa, Canada tak@doe.carleton.ca Abstract—Clock and data recovery (CDR) circuits using bang- bang phase detectors (BBPDs) are widely used in high speed serial links. The BBPD quantizes the phase difference between the input data and the recovered clock, generating a two state output for the loop filter (LF). The two-state output causes the behavior of the BBPD to be highly nonlinear and difficult to analyze. This paper provides a detailed analysis of the jitter transfer for second order bang-bang CDR circuits. Two popular representations of the second order bang-bang CDR circuits are used for our analysis. A detailed derivation of the jitter transfer expression is presented using each representation. Then a modified expression is derived, which is then verified by a phase-domain model implemented in Simulink. Simulation results show good agreement with the derived expression. Keywords- Bang-Bang, CDR, Clock and Data Recovery, jitter Transfer, Phase Detector. I. INTRODUCTION CDR circuits are critical components in high speed serial communication. Recently, bang-bang phase detectors (BBPDs) incorporated in CDR circuits have shown advantages over their linear counterparts. BBPDs have a simpler structure and they can operate at much higher speeds. However, the nonlinear behavior of BBPDs makes the analysis for jitter performance difficult. Several methods have been proposed for analyzing the nonlinear behavior of BBPDs [1-4]. Fig. 1 shows one representation for the second order bang-bang CDR circuit presented in [1]. This representation has two paths modelling the loop filter components. Equations were derived in [1] explaining the behavior of the loop by making an analogy with Delta modulation. A second representation, based on RC type analog filter, was used to analyze jitter performance, as shown in Fig. 2. In order to simplify the analysis, a piece- wise linear function was utilized in describing the behavior of the bang-bang CDR circuit. In this paper we will use both representations to analyze the jitter transfer characteristics for the second order bang-bang CDR circuit. Expressions for jitter transfer from [1] and [2] are presented and analyzed. A more accurate expression is derived and verified by simulation. Figure 1. Bang-bang CDR circuit block diagram with two paths. Figure 2. Bang-bang CDR circuit block diagram with analog filter. Figure 3. Jitter transfer curve. Section II includes a review of jitter transfer characteristics. In section III, we analyze the expression for jitter transfer based on the two CDR representations. Section IV presents the simulation results and in section V we conclude the paper. 2010 International Conference on Electronics and Information Engineering (ICEIE 2010) V2-40 Volume 2 C 978-1-4244-7681-7/$26.00 2010 IEEE