Session S3H 1-4244-1084-3/07/$25.00 ©2007 IEEE October 10 – 13, 2007, Milwaukee, WI 37 th ASEE/IEEE Frontiers in Education Conference S3H-8 BIST Analyzer: a Training Platform for SoC Testing A.Jutman 1 , A.Tsertov 1 , A.Tsepurov 1 , I.Aleksejev 1 , R.Ubar 1 , H.-D.Wuttke 2 1 Artur Jutman, Tallinn University of Technology, Department of Computer Engineering, Raja 15, Tallinn 12618, Estonia, artur@pld.ttu.ee Anton Tsertov, Tallinn University of Technology, Department of Computer Engineering, Raja 15, Tallinn 12618, Estonia, antonchertov@gmail.com Anton Tsepurov, Tallinn University of Technology, Department of Computer Engineering, Raja 15, Tallinn 12618, Estonia, anton.chepurov@gmail.com Igor Aleksejev, Tallinn University of Technology, Department of Computer Engineering, Raja 15, Tallinn 12618, Estonia, aleksejev.igor@gmail.com Raimund Ubar, Tallinn University of Technology, Department of Computer Engineering, Raja 15, Tallinn 12618, Estonia, raiub@pld.ttu.ee 2 Heinz-Dietrich Wuttke, Ilmenau Technical University, Faculty of Informatics and Automation, PO box 100565, D-98684 Ilmenau, wuttke@.tu-ilmenau.de Abstract - Linear Feedback Shift Registers (LFSR) and other Pseudo-Random Pattern Generators (PRPG) have become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers, and high-performance integrated circuits. The current paper describes a training and research tool for learning basic and advanced issues related to PRPG-based test pattern generation. Unlike other similar systems, this tool facilitates study of various test optimization problems, allows fault coverage analysis for different circuits and with different LFSR parameters. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The multi-platform JAVA runtime environment allows for easy access and usage of the tool both in a classroom and at home. The BIST Analyzer represents an integrated simulation, training, and research environment that supports both analytic and synthetic way of learning. Due to the above mentioned facts the tool provides a unique training platform to use in courses on electronic testing and design for testability. The BIST Analyzer has got a positive feedback from students of Darmstadt TU (Germany) and Tallinn TU (Estonia). Index Terms – Courses on electronic testing and design, Training and research tool, Web-based training, Java platform. INTRODUCTION Accordingly to the International Technology Roadmap for Semiconductors (ITRS) [1], the increasing complexity of recent VLSI circuits and transition to multi-core System-on- Chip (SoC) and Network-on-Chip (NoC) paradigms has made testing (including planning, test generation and scheduling) one of the most complicated and time-consuming problems in the domain of digital microelectronics. During the last several years, ITRS reports indicate that the semiconductor manufacturing industry is inevitably moving towards test compression and self-testing approaches that allow either to efficiently feed test data to individual system cores or to initially design self-testable cores. The key concepts applied in modern testing are based on data coding, data compression, cryptography, field theory, signature analysis, Boolean algebra, automata theory, linear programming, evolutionary optimization, solid-state physics and many-many other advanced areas of modern science and technology. Hence, the contemporary education in microelectronics must follow these latest industrial and research trends in order to supply the society with high-level engineers and researchers who feel themselves comfortable within this junction of different technologies, concepts and fields of knowledge. This paper presents a training system aimed at teaching main (both basic and advanced) principles and techniques applied in self-testing (BIST) of modern multi-core electronic systems. Unlike other similar systems [2], the “BIST Analyzer” facilitates study of various test optimization problems, allows fault coverage analysis for arbitrary circuits and with various test generation and optimization parameters. The tool illustrates the working principles of Pseudo-Random Test Pattern Generators (PRPG), gives students a hands-on experience on designing, optimizing and using them as a stand-alone solution as well as in combination with deterministic and other off-chip test generators. The tool is adapted for both analytic and synthetic study, where the students first learn the subject by observation (using prepared examples) and then generate and/or solve their own specific exercises. The training tool was designed accordingly to the concept of “Living Pictures” [3]. The main elements of this concept incorporate: graphical representation of the learning subject, dynamic content, user-friendly interface, concentration on the most important topics in the simplest possible way, easy action and reaction, and game-like style of learning. The same system could be used by teacher during a lecture for explaining a dynamic content as well as by students later at home when repeating and digesting the topic. In this way the dynamic part of the lecture will not be lost. Moreover, the same system could be used later - during tests and examinations. In order to make our software being easily available, we used the Java platform, which is supported by most operating systems. In the next section we provide necessary background about BIST and PRPG. The overview of the training tool modules and main GUI solutions is given in Sections 3 and 4 correspondingly. Section 5 describes extended training environment the BIST Analyzer becomes a part of. Summary and conclusions are given in Section 6.