IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 10, OCTOBER 2003 1767 An Integrated CMOS RF Synthesizer for 802.11a Wireless LAN Frank Herzel, Gunter Fischer, and Hans Gustat Abstract—A frequency synthesizer combining a relatively large tuning range (4.12–4.72 GHz) with a low noise sensitivity is presented. A stable fine-tuning loop is combined with an unstable coarse-tuning loop in parallel. As a result, a stable phase-locked loop (PLL) with a relatively wide tuning range and a moderate level of reference spurs is obtained. By adding a resistorless coarse-tuning loop, the tuning range was increased by a factor of four with no penalty in terms of phase noise, reference spurs, and settling speed. Also, the additional chip area and power consumption are negligible. The CMOS PLL circuit fabricated in a 0.25- m technology is aimed at multiband WLAN transceivers. Index Terms—Dual-loop phase-locked loop, frequency synthe- sizer, multiband transceiver, phase-locked loop (PLL), reference spurs, wireless LAN. I. INTRODUCTION I NTEGRATED phase-locked loops (PLLs) have to cope with variations in the device parameters with process and temper- ature resulting in frequency variations of the voltage-controlled oscillator (VCO). Therefore, the tuning range must be relatively large in order to cover the desired band and the VCO frequency variations. A still larger tuning range is required for multiband transceivers. For the 802.11a wireless LAN standard, for ex- ample, a tuning range from 4.12 to 4.66 GHz must be guaran- teed if the sliding IF architecture in [1] is used for both bands between 5.15 and 5.825 GHz. This translates into a high VCO gain increasing the sensitivity of the PLL with respect to noise in the control line. As a result, undesired frequency components (reference spurs) are created. This effect becomes yet more trou- blesome with technology scaling, since the supply voltage needs to be reduced increasing the required VCO gain. A VCO with two or more control ports [2] is useful is this context. One way to reduce the VCO gain while maintaining a moderate tuning range is to digitally switch between different capacitances in the res- onance circuit [3], [4]. Such a switched-capacitor tuning loop requires an array of capacitances which need to be controlled digitally. This extends the possible tuning range beyond the pos- sibilities of the available varactors. Another way to achieve both wide tuning range and low noise is to add a second feedback loop to the PLL [5]–[7]. The solution in [5] provides a contin- uous and wide tuning range, but the MOS transistors used for inductive VCO tuning add noise to the LC-VCO. PLLs for RF applications using dual-path active loop filters have been pre- sented in [6] and [7]. In our design, we combine a resistorless coarse-tuning loop with a stabilizing fine-tuning loop in par- allel without switching. The only components which need to be added to a standard PLL are a charge pump, a capacitor, and a coarse-tuning input for the VCO. Manuscript received April 8, 2003; revised June 23, 2003. The authors are with IHP Microelectronics, D-15236 Frankfurt (Oder), Ger- many (e-mail: herzel@ihp-microelectronics.com). Digital Object Identifier 10.1109/JSSC.2003.817601 (a) (b) Fig. 1. Schematic view of (a) the frequency synthesizer and (b) the VCO. II. PLL ARCHITECTURE Fig. 1 show schematic views of the frequency synthesizer and the VCO. The synthesizer is composed of two parallel loops sharing the same phase-frequency detector (PFD). The charge pump of the upper loop (current ) is capacitively loaded, while the charge pump of the lower loop (current ) is loaded with a capacitor and a resistor in series. A smaller capacitance is added in parallel to this RC combination. The VCO has two control inputs with the VCO gain or , respectively. A programmable frequency divider is inserted between the VCO output and the PFD input. The idea behind this topology is to use a relatively slow coarse-tuning loop with a large VCO gain in conjunction with a fast fine-tuning loop to ensure sta- bility. The gain of the fine-tuning loop can be much smaller than , resulting in a reduction of reference spurs which are roughly proportional to . The coarse-tuning loop also cre- ates reference spurs. Despite the high VCO gain, these can be well suppressed by a sufficiently large blocking capacitor , since no resistor is included in the coarse-tuning loop. While this 0018-9200/03$17.00 © 2003 IEEE