156 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 2, JUNE 1999 Universal Delay Test Sets for Logic Networks Uwe Sparmann, Member, IEEE, Holger M¨ uller, and Sudhakar M. Reddy, Fellow, IEEE Abstract—It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function , and checks any UGN realization of for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems. Index Terms— Delay test, design for testability, unate gate networks, universal test sets. I. INTRODUCTION T HE development of very large scale integration (VLSI) systems is driven by the demand for higher scale of integration and faster circuits. As a consequence, the suscepti- bility to manufacturing defects rises and reliability becomes a serious problem. In order to achieve a sufficient quality level of the shipped product, chips have to be checked not only to verify their static correctness, but also to guarantee their correct dynamic (temporal) behavior. Test-generation methods for checking the temporal correct- ness of a manufactured circuit have been studied considerably in the literature (see, e.g., [1]–[8]). They are mostly based on the gate [9] or path delay [10] fault model. Recently, the path delay fault model has been generalized by also considering path systems in case the speed of single paths cannot be checked robustly [11]. This approach has been successfully applied to derive less stringent necessary and sufficient conditions for the delay testability of two-level circuits. The above test-generation methods assume that the realiza- tion of the circuit is known a priori. Thus, a test set with near-minimal size can be computed. At the same time, since the test set is tailored to a specific design, even the smallest change in circuit structure may render it useless. Also, the test-generation process for a design-dependent delay test set is computationally very expensive. (In order to achieve complete fault coverage with respect to the path delay fault model, the number of paths which have to be considered may be Manuscript received May 22, 1995; revised September 6, 1998. This work was supported by the Deutsche Forschungegemeinschaft under Grant Sp431/1- 1 and under Grant SFB 124 VLSI Entwurfsmethoden und Parallelit¨ at. U. Sparmann and H. M¨ uller are with the Computer Science Department, University of Saarland, 66123 Saarbr¨ ucken, Germany. S. M. Reddy is with the Department of Electrical and Computer Engineer- ing, University of Iowa, Iowa City, IA 52242 USA. Publisher Item Identifier S 1063-8210(99)03339-9. exponential in the number of circuit inputs.) In addition, full testability with respect to the gate or path delay fault model is usually only achievable by extensive design for testability modifications or synthesis for testability (see, e.g., [12]–[16]), which often increase circuit size and can degrade circuit performance. The purpose of this paper is to show that for a large class of logic circuits, the unate gate networks (UGN’s) [17], the above problems can be eliminated, i.e., there exist easy to compute universal delay test sets, which only depend on the desired function, but not its specific UGN implementation. Previous results concerning the derivation of universal test sets for UGN’s [17]–[21] have been restricted to the multiple stuck- at and stuck-open fault model. Reddy, Betancourt, Akers, and Gupta and Jha have shown how to derive a universal test set for a given function , which checks any UGN realization of for multiple stuck-at faults [17]–[19] (all robustly testable stuck- open faults [20]). In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of the given function. This result implies that, for UGN’s, complete testability for delay faults can be guaranteed without any design for testability modifications. This is even true for UGN realizations which are not testable with respect to the gate or path delay fault model. In order to be able to prove the temporal correctness of such implementations, we pursue the approach of [11] and argue the correctness of whole path systems instead of individual paths. The notions and techniques developed in this context are not only of interest in the context of universal test sets, but also for more general settings [22]. There are various applications of our results. The first one is for testing of dynamic CMOS logic, which is often applied in high-speed circuits [23] and must be structured as an UGN. Also, self-checking circuits based on unordered codes are usually built as UGN’s [24], [25]. Another application is in the synthesis for delay fault testability. Any circuit can be transformed into an UGN of the same depth with, at most, doubling its size [17]. This implies a design for delay- testability method which does not compromise the speed of a given circuit implementation. Finally, it will be proven in this paper that, for delay testing of UGN’s, only two initialization vectors are sufficient. This fact can be applied in order to simplify a self test of UGN’s for delay faults. Experimental results given for ISCAS89 [26] and two-level Microelectronics Center of North Carolina (MCNC), Research Triangle Park, NC [27] benchmarks show that, for many functions, there exist efficient UGN implementations, and that the corresponding universal test sets are of reasonable size. 1063–8210/99$10.00  1999 IEEE