A Modular Memory BIST for Optimized Memory Repair Philipp Öhler 1 , Alberto Bosio 2 , Giorgio Di Natale 2 , and Sybille Hellebrand 1 1 University of Paderborn, Germany 2 LIRMM, University of Montpellier, France {oehler, sybille.hellebrand}@upb.de, {alberto.bosio, giorgio.dinatale}@lirmm.fr Abstract An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solu- tions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of test and repair and can be achieved with only small modifications in the BIST control. 1. Introduction Today system-on-chips (SoC) embed several hun- dreds of different memory cores occupying more than 90% of the SoC chip area. The yield of the entire system is therefore dominated by the memory yield. Memory test and repair capabilities are provided to check the functionality of the memory cores and to increase yield. In the presence of manufacturing de- fects, redundant elements can replace the failing parts of the memory array [1]. Various built-in self-repair (BISR) schemes have been developed [2, 3, 4]. In most of these schemes test and repair coexist. Meanwhile, implementing a memory BIST is possible by using intellectual prop- erty (IP) cores or by relying on automated generation flows of CAD tools. Memory repair requires the ex- act failure information in the cell array, and most repair schemes are flexible in the sense that any march-like test can be used for failure retrieval. Thus the memory BIST cores can be integrated into a test and repair infrastructure without any modification. The integrated test and repair approach presented in [4] supports an optimal built-in self-repair for memories with redundant rows and columns (“2D redundancy”). The scheme interleaves test and repair analysis to avoid large failure bitmaps. Moreover, it Part of this research has been performed within the framework of the DFG grant DIADEM (HE 1686/2-1). follows a depth first strategy for traversing the binary tree for spare allocation. This supports a hardware implementation scaling well with the number of spares. However, backtracking in the search tree re- quires a restart of the complete test. A more detailed analysis shows that repeating the complete the test may lead to an unnecessarily high increase in test time. To overcome this problem, the concept of a modular march test is introduced in this paper. 2. The Modular Test Strategy The interleaved test and repair scheme in [4] makes repair decisions as soon as faults are detected during test. The nodes in the search tree for the best repair configuration correspond to detected faults while the edges represent repair decisions (row or column). Backtracking is necessary when a chosen path cannot provide a solution or to prove that an already found solution is optimal. In Figure 1 an ex- ample is given. Figure 1: Partial search tree during repair analysis The information attached to node x shows that a fault at address a(x) has been detected, and the edge (x, y) indicates a row repair. If backtracking to node x occurs, then the test is restarted to determine the re- maining faults for the alternative repair decision using a column. This avoids the need for large failure bitmaps, but a complete restart after each backtrack implies a high time penalty. If a march test with march elements M 0 , ..., M n is used, then the information during which march ele- ment a fault has been detected can help to reduce the overall test and repair time. In Figure 1, the fault at node x has been detected during march element M i , 14th IEEE International On-Line Testing Symposium 2008 978-0-7695-3264-6/08 $25.00 © 2008 IEEE DOI 10.1109/IOLTS.2008.30 171 14th IEEE International On-Line Testing Symposium 2008 978-0-7695-3264-6/08 $25.00 © 2008 IEEE DOI 10.1109/IOLTS.2008.30 171 Authorized licensed use limited to: IEEE Xplore. Downloaded on February 24, 2009 at 06:03 from IEEE Xplore. Restrictions apply.