22 nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007 - 1 - A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction Sybille Hellebrand University of Paderborn Christian G. Zoellin, Hans-Joachim Wunderlich University of Stuttgart Stefan Ludwig, Torsten Coym, Bernd Straube Fraunhofer IIS-EAS Dresden Abstract Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output of a gate, which in turn can propagate to a register and cause a single event upset (SEU) there. Circuit level modeling and analysis of SETs provides an attractive compromise between computationally expensive simulations at device level and less accurate techniques at higher levels. At the circuit level particle strikes crossing a pn-junction are traditionally modeled with the help of a transient current source. However, the common models assume a constant voltage across the pn-junction, which may lead to inaccurate predictions concerning the shape of expected glitches. To overcome this problem, a refined circuit level model for strikes through pn-junctions is investigated and validated in this paper. The refined model yields significantly different results than common models. This has a considerable impact on SEU prediction, which is confirmed by extensive simulations at gate level. In most cases, the refined, more realistic, model reveals an almost doubled risk of a system failure after an SET. 1. Introduction Nowadays, a saturation of the soft error rate (SER) in memories can be observed, while technology scaling has led to an increased vulnerability of combinational logic and latches. Soft error mitigation for random logic has become a topic of major importance [1, 13, 23, 26]. Here, a wide spectrum of strategies is possible, such as voltage scaling, robust flip-flop design, selec- tive hardening or self-checking circuit design. However, in order to choose the best approach for a certain application and to determine the necessary degree of protection, effective tech- niques are needed for characterizing a circuit’s sensitivity to soft errors as accurately as possible. A particle strike in combinational logic can cause a glitch in the output voltage of a logic gate. Usually such a “single event transient” (SET) only leads to a system failure, if it can propagate to a register and turn into an SEU there. As a precondition, propagation paths must be sensitized in the logic, and the glitch must arrive at the register during a latch window [18, 24]. But, depending on the amplitude and the duration of a glitch, its propagation can also be prevented by electrical masking [8]. Thus, it is particularly important not only to predict the occurrence of an SET but also to accurately characterize its expected shape. State of the art device simulators allow a precise characterization of SETs, but they are also highly computationally intensive [9]. In many cases circuit level techniques offer a good compromise between accuracy and computational cost [2, 17, 19, 25]. Mixed-level approaches combine device level analysis for a few devices with circuit level analysis for the rest of the circuit [8, 9].