INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. 2011; 39:1–15 Published online 22 June 2009 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.610 Digital architectures realizing piecewise-linear multivariate functions: Two FPGA implementations Marco Storace ∗, † and Tomaso Poggi Biophysical and Electronic Engineering Department, University of Genoa, Via Opera Pia 11a, I-16145 Genova, Italy SUMMARY Digital architectures for the circuit realization of multivariate piecewise-linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n-dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three-variate static functions and one concerning a dynamical control system defined by a bi-variate PWL function. Copyright  2009 John Wiley & Sons, Ltd. Received 16 December 2008; Revised 20 April 2009; Accepted 25 April 2009 KEY WORDS: piecewise-linear functions; digital architecture; FPGA; nonlinear circuit 1. INTRODUCTION This paper is concerned with digital architectures implementing piecewise-linear (PWL) ‡ functions depending on two or more inputs. This kind of architectures may have many practical applica- tions, mainly in the field of real-time embedded control systems—either adaptive [1] or based on fuzzy logic. § Reference [3]—or whenever it is not feasible or convenient resorting to computers or other general-purpose devices, such as DSP boards. In particular, these architectures would be adequate for implementation on either FPGAs (e.g. by exploiting hardware resources already existing in an embedded system) or on VLSI circuits characterized by small size (few mm 2 ) and/or low-power consumption (few mW) and/or response times in the order of ns or us. The literature numbers many works concerning representations of PWL multivariate functions (see [4–6] and references therein). Other works (see [7–14] and references therein) concern both dedicated hardware implementations (analog or digital) and hardware/software implementations of these functions. This paper is focused on the circuit implementation of PWL n-variate continuous functions f PWL defined over compact domains and is based on the high-level architecture proposed in [15]. This mixed-signal architecture is based on a PWL approximation technique [16, 17] and provides PWL input–output relationships defined over compact domains uniformly partitioned into simplices. Each PWL function f PWL is linear over any simplex and is expressed as a weighted sum of locally ∗ Correspondence to: Marco Storace, Biophysical and Electronic Engineering Department, University of Genoa, Via Opera Pia 11a, I-16145 Genova, Italy. † E-mail: marco.storace@unige.it ‡ In this paper, PWL is meant to be equivalent to piecewise-affine. § The relationship between fuzzy systems and PWL interpolators were investigated in [2]. Copyright  2009 John Wiley & Sons, Ltd.