A Simulation Methodology for a NoC-Based Dynamically Reconfigurable System Mario Raffo, Marius Strum, Wang Jiang Chau Electronic Systems Department, School of Engineering University of São Paulo (USP) São Paulo, Brazil {mraffo,strum,jcwang}@lme.usp.br Abstract— The dynamic reconfigurable system (DRS) are important solutions based on partially reconfigurable FPGAs that allows larger flexibility, and reduction in area and power. The run-time reconfiguration has not become a mainstream activity though, due to the lack of solid design methodologies and associated tools. One of the approaches aimed to free the designer of lower level implementation details is to use structured communication resources to provide the interaction between reconfigurable partitions (modules). In this paper, we present the architecture of a network-on-chip (NoC) based dynamically reconfigurable system and a simulation methodology. The simulation is based on the dynamic circuit switching (DCS) technique and allows us do the verification of all system operation time. Keywords-component; Dynamic reconfigurable systems; Network on Chip;-Dynamic Circuit Switching. I. INTRODUCTION In recent years, SRAM-based Dynamic or Run-Time Reconfiguration (RTR) FPGAs (DRFPGAs) have been accepted as an important and potential alternative for lowering costs of digital circuits, especially regarding the flexibility in rapidly changing the functions being performed and reducing area consumption [1]. They have the ability of partially reconfiguring the implemented module functionality during execution, making improvements on functional density. However, they add new dimensions to the System on Programmable Chip (SoPC) design space, due to the different possibilities of physical, temporal and functional partitions of the original application and due to the possibility to use different devices available on the market. Although new methodologies and tools have been proposed in recent years [2- 6] to deal with the increased design complexity of this class of circuits, the design solutions are still very ad-hoc. One of the problems to be solved is the communication between reconfigurable partitions or modules, what includes the data retention, the bus-macros signals management and the characterization of latency effects due to the reconfiguration cycle. To deal with these problems, structured communication resources have been proposed. A standard model for communication between the modules frees the designer from the design details of dynamic reconfigurable systems (DRSs), allowing the designer to focus on wrappers and computing logic, reducing the design effort. Different works have been reported for both bus-based [2,3] and network-on-chip (NoC) based [4-6] implementations for DRS communication. Bus-based systems have the drawback of lack of parallelism, with a limited performance since the bandwidth is shared between several system components. NoCs provide the transfer of packets of information through a more complex switching scheme, but potentially with better performance for systems with large number of components. They support parallel communication, besides presenting high scalability and modularity. NoCs are also quite interesting for DRFPGAs since their typical bi-dimensional structure matches the partial reconfiguration architecture and capabilities of recent FPGAs families (Virtex 4 and 5) [7], for which, the managing of arbitrary sized rectangular partition in the fabric is possible. In the above works for structured communication-based DRS approaches, architectural and some specific implementation aspects have been reported, but with little indication on design methodologies or tools for their use. Unfortunately, the design flow of a DRS based on NoCs turns to be longer than a traditional non-dynamically reconfigurable one, due to the lack of design aids. One of the extra tasks brought up by DRSs on designers is the need to assure that the intended specification is maintained in the partitioned RTL implementation; new set of simulations must be run thoroughly, with the inclusion of the effects of bus-macros between processing elements and NoC routers, and of the delay related to the bitstream upload [8-11]. Although, it is recognized that a careful verification process is mandatory in order to create confidence on the design of current high complexity systems, the topic on DRSs simulation has not received the needed attention. The first important simulation technique in this area was proposed by Lysaght [8] with the Dynamic Circuit Switching (DCS), by which, isolation switches are used to model the action of bus-macros and to allow the inclusion of reconfiguration time. Some modifications to the isolation switches were introduced in latter work [9], with VHDL signals values, like 0,1 and X,