Diamond and Related Materials 12 (2003) 1220–1223 0925-9635/03/$ - see front matter  2003 Elsevier Science B.V. All rights reserved. PII: S0925-9635 Ž 02 . 00384-9 Optimal layout for 6H–SiC VJFET controlled current limiting device D. Tournier *, X. Jorda , Ph. Godignon , D. Planson , J.P. Chante , F. Sarrus a,b, a a b b c Centro Nacional de Microelectronica (CNM), Campus UAB, Bellaterra, Spain a Centre de Genie Electrique de Lyon (CEGELY), Villeurbanne, France b ´ Ferraz Shawmut, Newburyport, MA, USA c Abstract SiC-based devices are very suitable for high current and high voltage applications wH. Matsunami, Progress in wide bandgap semiconductor SiC for power devices, Invited Paper, ISPSD’00 22–25 May 2000, Toulousex. Nevertheless, SiC material has some limitations that constrain the capability of these devices. This work is devoted to the design and fabrication of a new etched VJFET, which implements both gate and source in buried layers. This technological approach enables more flexibility in the basic cell layout design (square cells) than the conventional surface gate implementation. Therefore, various geometrical layouts have been investigated in order to find a trade-off between current density, driving ability and current limiting capability. Theminimum lithography feature, reactive ion etching and the minimum spacing between adjacent implantations were key points in setting-up the design rules. I –V curves of the designed structures for a gate-to-source bias of 0 and y30 V has been performed at room temperature. All devices exhibit a current saturation at an on-state voltage higher than 10 V. The dependence of the internal access gate resistance on the layout has been checked by means of transconductance measurements. Transconductance has been estimated for each type of structure, being in the range of 57.8–672 mSymm. Nevertheless, a new figure of merit (the transconductance per active area) allows to find out the most suitable layout in terms of output current density and gate resistance. A comparison in terms of current and transconductance per source gives the best solution in terms of output saturation current and gate resistance. The results of those measurements are discussed with future perspectives for implementation of the most appropriated layout in an integrated system.  2003 Elsevier Science B.V. All rights reserved. Keywords: JFET; Serial protection device; 6H–SiC; Reactive ion etching; Characterization; Integration 1. Introduction Limitations of SiC devices, among others, lie on the quality of silicon carbide substrates, which contain a large defect density such as micro pipes and dislocations, and also on some technological aspects such as the gate oxide growth for inversion channel implementation. A promising application of SiC-based devices are the current limiting devices for power system protection w1,2x, which benefits from its high thermal conductivity and wide band gap. VJFET structure has been chosen to avoid current SiC MOSFET limitation due to the low channel mobility. Layout study and process fabrication are first presented. Key point such as high-energy implantation and reactive ion etching (RIE) are then *Corresponding author. Tel.: q49-451-500-2402; fax: q49-451- 500-6279. E-mail address: tournier@cegely.insa-lyon.fr (D. Tournier). discussed. Eventually, electrical measurements are pre- sented in case of different layouts of structure. In conclusion a new device layout is then suggested. 2. Specific buried layer implementation Integration of devices is usually a challenge in term of current density. This argument is the key point considering silicon carbide technology, as the usable area are very small due to residual defects (micro pipes, dislocations,«), reducing wafer yield. In that way, a VJFET structure w3x with both gate and source buried layer (Fig. 1) was preferred to conventional surface gate implementation. The distribution of both source and gate buried layer authorizes a reduction of metal surface area used. Having buried layers allows to reduce surface metal connection and stacks levels. Thus, the necessary mask level number can be reduced. This specific gate and source implementation (Fig. 2) allows the fabrica-