D zyxwvutsrqponmlkjihgfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA CMOS scaling y.-J. Mii into the 21 st century: 0.1 zyx pm by Y. Taur D. J. Frank H.-S. Wong D. A. Buchanan S. J. Wind S. A. Rishton G. A. Sai-Halasz E. J. Nowak and ~ beyond This paper describes the design, fabrication, and characterization of 0.1 -pm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2x performance gain over 2.54, 0.25-pm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20x reduction in active power per circuit is obtained at a supply voltage e1 V with the same delay as the 0.25-pm CMOS. These results demonstrate the feasibility of high- performance and low-power room-temperature 0.1-pm CMOS technology. Beyond 0.1 pm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed. 1. Introduction zyxwvutsrq The evolution of MOSFET technology has been governed mainly by device scaling [l] over the past twenty years. One of the key questions concerning future ULSI technology is whether MOSFET devices can be scaled to 0.1-pm channel length and beyond for continuing density and performance improvement zyxw [2]. A number of device and technology issues will ultimately determine the limit of room-temperature scaling. Among the device issues are choice of power supply and threshold voltages versus active power and off-current requirements, control of short-channel effect, and hot-carrier reliability. Among the technology issues are ultrathin gate oxide, p+-polysilicon gate for surface-channel p-MOSFET, shallow source-drain junctions with low series resistance, and sub-0.2-pm lithography. In ideal constant-field scaling, both the power supply and threshold voltages should scale linearly with channel length. However, because of subthreshold nonscaling, the threshold voltage cannot be reduced without limit. Figure 1 shows the trend of power supply voltage, threshold voltage, and gate oxide thickness scaling versus channel length [3-51 from a mature 1-pm CMOS technology to a projected 0.1-pm CMOS technology. When the channel length is scaled down, the power supply voltage must be reduced as well to keep the device power and field (reliability) in reasonable limits. On the other hand, the threshold voltage has not been scaled in proportion to the power supply voltage. This is because the subthreshold slope, a measure of the transistor turn-off rate versus gate voltage, is largely driven by thermally activated diffusion Wopyright 1995 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the zyxwvutsrqponm Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other portion of this paper must he obtained from the Editor. 0018-8646/95/$3.00 Q 1995 IBM IBM J. RES. DEVELOP. VOL. 39 NO. 112 JANUARYiMARCH 1995 Y. TAUR ET AL.