Proceedings of the 6th International Caribbean Conference on Devices, Circuits and Systems, Mexico, Apr. 26-28, 2006 Nonlinearity Analysis of FinFETs A. Cerdeira', M. Aleman', V. Kilchitska2, N. Collaert3, K. De Meyer3 and D. Flandre2 1 Section of Solid State Electronics, Department of Electrical Engineering, CINVESTAV, Av. IPN No. 2508, A. P. 14-740, 07300 MEXICO D.F. (email: cerdeira@cinvestav.mx) 2 Microelectronics Lab, Universite catholique de Louvain (UCL), Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium (email: denis.flandre@uclouvain.be ) 3IMEC, Kapeldreef 75, B-3001, Belgium (email: collaert@imec.be) Abstract - Double-gate MOS transistors and their vertical version, FinFETs, are very promising for integrated circuit low signal analog applications. In this paper we present, for the first time, the nonlinearity analysis of this type of devices which complements the already done studies about the advantages and possibilities of FinFET for analog application. The analysis was done using the transfer DC characteristics in saturation, calculating THD and HD3 by the Integral Function Method. Complementary figures-of-merit THD/Avo and HD3/Avo were also calculated. FinFETs of different channel lengths and different Fin widths were studied. Results are compared with those obtained for single-gate fully-depleted (FD) SOI MOSFETs with HALO. From the present study we can conclude that analyzed FinFETs can have better or worse nonlinearity behavior than FD SOI MOSFETs with HALO depending on the operating conditions. Keywords - FinFET, double-gate MOSFET, harmonic distortion, nonlinearity analysis I. INTRODUCTION It is widely accepted that multigate MOSFETs are the most promising candidates for the requirements of new generations of analog and digital integrated circuits, where the scaling possibilities are of great importance. The double-gate transistors and their vertical version, the FinFETs, are widely studied [1,2], especially for their advantages and possibilities in low signal analog applications. As a complementary analysis, the study of the nonlinearity of this new type of device is very important. This analysis was made using the figures of merit of total harmonic distortion (THD), harmonic distortion of third order (HD3) and the ratios of THD and HD3 to the intrinsic gain Avo (i.e. THD/Avo and HD3/Avo) for transistors operating in saturation regime at fixed drain voltage. The distortion analysis was done using the Integral Function Method (IFM) which requires only the DC transfer characteristic under the analyzed conditions and can be applied for high nonlinearity cases [3]. In order to compare FinFET transistors with other competitive devices for low signal analog applications, single- gate fully depleted (FD) SOI MOSFETs with HALO doping against short-channel effects and similar dimensions were also analyzed. II. DEVICES UNDER STUDY The FinFETs devices under study are the same as presented in [2]. We analyzed two types of FinFETs; the first type has 66 Fins with a Fin width (WFIN) of 35 nm and Fin height (HFIN) of 75 nm, resulting in a channel width per Fin of 150 nm (estimated as W=2*HFin) with total channel width of 9.9 pm,. The Fin gate oxide thickness is 2 nm, the doping concentration is in the order of 6x1017 cm3, and in this case the Silicon Fin is fully inverted, although the conduction predominantly takes place only near the lateral interfaces, which present increased mobility degradation [2]. The values of the threshold voltage VT, determined by double-derivative method, are shown in Table 1. The studied channel lengths were: 70 nm, 110 nm, 0.5 pm, 1 pm, 5 pm and 10 pm. The transfer characteristics at VDS= 1 V are presented in Fig. 1. To make a fair comparison between different types of devices, the gate voltage overdrive (VGT=VG-VT) was used as variable. 3.0 - 2 5 - ,: 1.5- -j x,. C,) __p 1.0 - 0.5 - u -0.5 0.0 0.5 1.0 1.5 VGT [V] Figure 1. Measured FinFET transfer characteristics in saturation at VDS=IV for different channel lengths. The second type of analyzed FinFETs has a fixed channel length of 10 gm and one Fin. Devices with different WFIN of 60 nm, 80 nm, 100 nm, 200 nm, 300 nm, 0.5 gm and 10 gm were characterized. Their transfer characteristics in saturation at VDS= 1 V are shown in Fig. 2 and their threshold voltages are shown in Table 1. In this case if the WFIN is smaller than 70 nm, the transistor behaves as fully depleted; for higher WFIN it 1-4244-0041-4/06/$20.00 ©2006 IEEE. L [tm] FinFET 0.07 W=9.9 im ----0.11 ------ 0.5 VDS =1 V ...... 10 // / . . / . 9