A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS Suat U. Ay Received: 6 April 2010 / Revised: 2 August 2010 / Accepted: 4 August 2010 / Published online: 15 August 2010 Ó Springer Science+Business Media, LLC 2010 Abstract This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and sup- ply boosted (SB) circuits including level shifter, compar- ator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-V t MOSFETs. A 10- bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 lm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are ?0.8 and -0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/ conversion-step. Proposed supply boosting technique improves input common mode range of both SB compar- ator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process. Keywords Supply boosting technique  Analog-digital converter  SAR  Low-power  Supply boosted comparator 1 Introduction Supply voltage and power consumption of mixed-signal circuits and systems in energy-limited applications such as self-powered wireless sensor networks, portable biosignal acquisition devices, and energy-harvesting systems are critical. Efficiency degradation due to the sub-threshold leakage current inherent in advanced sub-100 nm CMOS technologies has to be addressed if they are used in energy- limited applications [1]. Besides, threshold voltages have not been scaled as fast as the supply voltages in these advanced processes making analog design challenging in sub-1 Volt supply voltages while accommodating both low-power consumption and wide input range operation. Power consumption and input range are the critical design parameters for most analog to digital converters (ADCs) in sub-1 V applications. A possible solution might be to design sub-1 V analog/mixed-signal circuits by exploring new circuit design techniques while using low cost, mature, and relatively low leakage standard CMOS technologies (typically L min [ 150 nm). Few of them have been pub- lished including bootstrapping [2], charge pump based circuits [3–5], switched opamp technique [6], floating gate based circuits [7], and threshold modulation tech- niques [8, 9]. Low-leakage mature CMOS processes have their own drawbacks especially for sub-1 V supplies. Typically, the sum of threshold voltages of NMOS and PMOS devices in these processes are in the order of 1 V or more which makes analog design challenging. This is mainly due to the reduced overdrive voltages for active MOSFET transistors. Operating these devices in weak inversion region or using unique circuit design techniques are currently used to address overdrive issue with the expense of speed, com- plexity, and size. S. U. Ay (&) Electrical and Computer Engineering, University of Idaho, Moscow, ID, USA e-mail: suatay@uidaho.edu 123 Analog Integr Circ Sig Process (2011) 66:213–221 DOI 10.1007/s10470-010-9515-3