Static-Noise Margin Analysis during Read Operation of 6T SRAM Cells B. Alorda, G. Torrens, S. Bota and J. Segura Univ. de les Illes Balears, Dept. Fisica, Cra. Valldemossa, km. 7.5, 07071 Palma de Mallorca, Spain e-mail: tomeu.alorda@uib.es Abstract SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word- and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing current leakage, as opposed to current methods that improve cell read stability at the cost of leakage increase. 1. Introduction During the past decades CMOS IC technologies have been constantly scaled down aggressively entering in the nanometer regime during this decade. Among the wide variety of circuit applications, integrated memories – and specially SRAM cell layout – has been significantly improved. It is well known that critical dimension (CD) reduction entails an increase in physical parameters variation, which among other effects has a direct impact on SRAM cell stability. Polysilicon and diffusion CD together with implant variations are the main causes of mismatch in SRAM cells. Current System on Chip (SoC) trends result in a significant percentage of the total die area being dedicated to memory blocks, thus making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc. Therefore, a deep knowledge and analysis about the stability of the SRAM cells and the impact of physical parameters variation is becoming a must in modern CMOS designs. The stability and robustness of a given SRAM cell is usually evaluated analyzing both its dynamic and static behavior during the typical operations: write, read and hold periods. According to this, the memory cell stability can be estimated from the Static Noise Margin analysis. SNM is defined as the minimum DC noise voltage needed to flip the cell state [1], and is used to quantify the stability of a SRAM cell using a static approach. A significant effort has been devoted to explore the impact of process variations, temperature, etc., using the SNM as a metric. In this paper we present a detailed analysis about 6T SRAM cells static stability during read, and compare the differences between SNM during hold- and read- mode. The read-mode is usually identified as the cell weakest mode. We investigate the impact of corner analysis to determine the worst-case using a commercial 65nm CMOS technology. The impact on SNM when voltage operations, temperature and power supply vary, is analyzed. The rest of the paper is organized as follows: the next section provides a SRAM cell stability background introducing the SNM parameter in detail. Section 3 explores the impact of variations on read-mode SNM. The section introduces a new approach that improves the cell stability by adjusting the nominal values of internal voltages during read operations. Some new ideas of increasing SNM during read operations are proposed and the relationship between cell stability and current behaviour are determined. Finally Section 4 points out the main conclusions of this work. 2. 6T CMOS SRAM STABILITY Figure 1. 6T SRAM cell schematic. The conventional 6T SRAM memory cell is composed of two cross-coupled CMOS inverters with two pass transistors connected to complementary bit-lines. Fig. 1 shows this well- known architecture, where the access transistors AXR and AXL are connected to the word-line (WL) to perform the access write and read operations thought the column bit-lines (BL and BLB). Bit-lines act as input/output nodes carrying the data from SRAM cells to a sense amplifier during read operation, or from write circuitry to the memory cells during write operations. All transistors have