Static and Dynamic Stability Improvement Strategies for 6T CMOS Low-power SRAMs B. Alorda, G. Torrens, S. Bota, J. Segura Electronic Systems Group, Physics Dept. Illes Balears University Palma de Mallorca, Spain tomeu.alorda@uib.es Abstract—The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, the Word-line modulation technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided. Keywords-Nanometre SRAM; Critical Charge; Static Noise Margin. I. INTRODUCTION During the past decades CMOS IC technologies have been constantly scaled down aggressively entering in the nanometer regime during this decade. Among the wide variety of circuit applications, integrated memories – and specially SRAM cell layout – has been significantly reduced. It is well known that dimension reduction entails an increase in physical parameters variation, which among other effects has a direct impact on SRAM cell stability. Polysilicon and diffusion critical dimensions (CD) together with implant variations are the main causes of mismatch in SRAM cells. Current System on Chip (SoC) trends result in a significant percentage of the total die area being dedicated to memory blocks, thus making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc... Therefore a deep knowledge and analysis about the stability of the SRAM cells and the impact of physical parameters variation is becoming a must in modern CMOS designs. The stability and robustness of a given SRAM cell is usually evaluated analyzing both its dynamic and static behavior during the typical operations: write, read and hold periods. According to this, the memory cell stability has been considered, in this work, as a combination of two parameters: Static Noise Margin (SNM) and Critical Charge (Q crit ). The SNM is the minimum DC noise voltage needed to flip the cell state [1], and is used to quantify the stability of an SRAM cell using a static approach during hold, read and write operations. A significant effort has been devoted to explore the impact of process variations, temperature, etc., using the SNM as a metric. Although SNM evaluate the static stability, it is not enough. The nature of SNM analysis is not adequate to evaluate the dynamic stability of cells. For that reason, the dynamic robustness of SRAM cells has to be evaluated through another well-known parameter referred to as the Critical Charge (Q crit ). The Q crit parameter quantifies the cell robustness in front of dynamic-events, being the amount of charge that must be collect by a node to flip the cell [2]. This parameter has been used extensively in soft-error rate evaluations due to particle impacts, but it may be used to extend the static stability analysis into the dynamic domain. So, in this paper, both parameters are used to propose different methodologies for SRAM 6T cell stability enhancement. We present a thorough analysis about 6T SRAM cells dynamic and static stability, and propose a new technique that enhances significantly cell robustness (both static and dynamic) when the cell is in its weakest state (read operation). Read- access disturbs can be decreased by reducing the amount of charge injection from the V DD -precharged bit-line to the cell node being low. This can be achieved mainly using three alternatives: read time reduction, cell structure modification and supply voltage modulation. The first technique makes the read time as short as possible to minimize the cell value distortion. It requires designing a fast sense-amplifier and adequate memory array architecture to reduce the bit-line capacitance. Cell structure modifications increase the number of cell transistors, i.e. 10T-cell [6], or 8T-cell [7] approaches, or introduce some new active elements to help unstable cells [4] in low-power environments. Unstable cells are especially vulnerable during the half-selected operations (half-selected columns are those columns whose cells share word-line selection, but are neither written nor read out during operation). The third alternative is related to maintaining the power supply voltage as high as possible to achieve the higher SNM values while reducing its value during hold periods to decrease current leakage [8, 9]. We investigate a technique valid for nanometer-based layouts based on a dual voltage scheme to drive the word line. The proposed solution can be used to improve both write and read stability while achieving a bit-cell layout that mitigates the 978-3-9810801-6-2/DATE10 © 2010 EDAA