To appear in Journal of Embedded Computing, 2004. Control-Scheduling Codesign of Real-Time Systems: The Control Server Approach Anton Cervin Department of Automatic Control Lund Institute of Technology Box 118, SE-221 00 Lund, Sweden anton@control.lth.se Johan Eker Research Department Ericsson Mobile Platforms AB SE-221 83 Lund, Sweden johan.eker@emp.ericsson.se Abstract The paper presents the control server, a real-time scheduling mechanism tailored to control and signal processing applications. A control server creates the abstraction of a control task with a specified period and a fixed input-output latency shorter than the period. Individual tasks can be combined into more complex components without loss of their individual guaranteed fixed-latency properties. I/O occurs at fixed predefined points in time, at which inputs are read or controller outputs become visible. The control server model is especially suited for codesign of real- time control systems. The single parameter linking the scheduling design and the controller design is the task utilization factor. The proposed server is an extension of the constant bandwidth server, which is based on the earliest-deadline-first scheduling algorithm. The server has been implemented in a real-time kernel and has also been validated in control experiments on a ball and beam process. 1. Introduction The design of a real-time control system is essen- tially a codesign problem. Decisions made in the real- time design affect the control design, and vice versa. For instance, the choice of scheduling policy influ- ences the latency distributions in the control loops, and, ideally, this should be taken into account in the control design. At the same time, the performance requirements of the individual control loops place de- mands on the real-time system with regard to sam- pling periods, latencies, and jitter. Traditional scheduling models give poor support for codesign of multi-threaded real-time control systems. One difficulty lies in the nonlinearity in schedul- ing mechanisms such as rate-monotonic (RM) or earliest-deadline-first (EDF) scheduling: a small change in a task parameter—e.g., period, execution time, deadline, or priority—may give rise to unpre- dictable results in terms of input-output latency and jitter. This is crucial, since the performance of a con- troller depends not only on its sampling period, but also on the latency and the jitter. In the control de- sign, it is straight-forward to account for a constant latency, while it is difficult to address varying or un- known delays. In the seminal Liu and Layland paper [Liu and Layland, 1973], it is assumed that I/O is performed periodically by hardware functions, introducing a one-sample delay in all control loops closed over the computer. This scheme does provide a quite nice separation between the scheduling design and the control design. From a scheduling perspective, the controller can be described by a periodic task with a period T , a computation time C, and a deadline D = T . From a control perspective, the controller will have a sampling period of T and a constant latency L = T . This allows the control design and the real-time design to be carried out in relative isolation. However, the one-sample latency degrades the con- trol performance and is ultimately a waste of re- sources. A common alternative implementation is therefore to perform the I/O requests within the task loop and output the control signal as soon as possi- ble in each period (e.g., [Klein et al., 1993, Åström and Wittenmark, 1997]). At this point, however, the design problem becomes very complicated. The I/O jitter and latency of a controller are now affected by variations in its own execution time as well as in- terference from higher-priority tasks (which in turn depend on the variations in the task execution times, the phasing of the periodic tasks, the arrival pattern of sporadic tasks, etc.). In the best case, it may be possible to derive formulas for the worst-case and best-case response times of the tasks (e.g., [Auds- ley et al., 1993,Redell and Sanfridson, 2002]), but this information is still not sufficient to accurately predict the performance of the controllers. Further- more, as argued in [Jeffay and Goddard, 2001], with standard RM and EDF scheduling it can be difficult