48 International Journal of Mechanical and Materials Engineering (IJMME), Vol. 2 (2007), No. 1, 48-54. UNDER BUMP METALLURGY (UBM)-A TECHNOLOGY REVIEW FOR FLIP CHIP PACKAGING M.K. Md Arshad 1 , U. Hashim 1 , Muzamir Isa 2 Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM) 1 PPK Mikroelektronik, 2 PPK Sistem Elektrik Blok A-Pusat Pengajian Jejawi Jalan Kangar-Arau 02600 Arau, PERLIS. E-mail: mohd.khairuddin@kukum.edu.my ABSTRACT Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size and lower cost of electronic consumer products. Wafer bumping is unavoidable process in flip chip packaging, thus, picking the correct bumping technology that is capable of bumping silicon wafer at high yield and a high reliability with lower cost is challenging. This paper discusses the available wafer bumping technologies for flip chip packaging. The discussion will be focused on process assembly, solder ball compatibility, design structure and lastly cost which translated to overall product costs. Keywords: Flip chip Technology, Wafer Bumping, Flip chip packaging INTRODUCTION The goal of modern semiconductor packaging is to achieve shorter electron pathways for increased speed, lower power, better device functionality and lower cost. Flip chip is proving itself to meet these demands. Flip chip is not a new technology that has just recently come in the market. The first flip chip was introduced by IBM in the late 1960’s is known as Controlled Collapse Chip Connection (C4) [1, 2]. This collapsible technology was limited to typical higher temperature solder utilizing high solder leads (97Pb/Sn and 95Pb/Sn) that were joined to ceramic package. With the rapid growth in the flip chip market, the technology has gone through several revolutions, from the ceramic to plastic package, from the high leads to eutectic 63Sn/Pb and nowadays, leaded free [3]. However, the major driven factor is still cost reduction in electronic consumer product that directly related to flip chip package. Flip chip fabrication process involved of several sequential steps: wafer bumping, attaching the bump die to the board or substrate and then completing the assembly with an adhesive underfill. In wafer bumping, it comprised of two functional steps. The first step is to create a solderable metal surface for each of the input/output (I/O) that serve as an interface between the I/O pad and the solder bump known as under bump metallurgy (UBM). The UBM is also known as multilayer thin film between aluminum bond (I/O) pad, passivation and solder bump as shown in Fig. 1. It can be deposited through evaporated, sputtered, electroplated or electroless techniques [4-6]. The second step is deposition of solder ball of which provides for both mechanical and electrical connection between the die and the substrate. Among of these techniques, electroless nickel immersion gold (ENiG) under bump metallurgy was rigorously studied because it can provide lower cost and Pb-Free solutions [4 - 11]. Fig. 1. Schematic diagram of (a) flip chip package (b) Under Bump Metallurgy (UBM) (a) (b)