Extraction and Representation of a Supervisor Using Guards in Extended Finite Automata S. Miremadi, K. Åkesson and B. Lennartson Department of Signals and Systems, Chalmers University of Technology SE-412 96 Göteborg, Sweden {miremads, knut, bengt.lennartson}@chalmers.se Abstract— In supervisory control theory, an issue that often arises in real industrial applications is the huge number of states for the supervisor, which requires a lot of memory. Another problem that is typically encountered for the users of supervi- sory synthesis tools is lack of information and unreadability of the supervisor. In this paper, we introduce a method to characterize a controllable and non-blocking supervisor directly on the modular automata (sub-plants and sub-specifications), by extracting some guard conditions from the synthesized supervisor and the synchronized automaton. Thus, the pre- sented approach may potentially model a complex supervisor using a compact representation whilst not infringe the original modular structure. Furthermore, the guard conditions, which are generated from a set of states, may give the user of the synthesis procedure a better understanding of which states that were removed during the synthesis. In order to obtain more compact guard expressions, we include some unnecessary states (unreachable and extended forbidden states) in the set of states that will be used for guard generation. By exploiting this extra information, it is possible to reduce the logical expressions to more compact guard conditions. I. INTRODUCTION In the last decades, there has been a lot of effort to design controllers for complex systems automatically. One approach suggested by Wonham and Ramadge, is the Su- pervisory control theory for discrete event systems [1]. It is a framework for automatically synthesizing a discrete event supervisor for a plant so that the closed-loop system fulfills given specifications. The plant and the specifications are most often modeled by finite state automata. Both the plant and the supervisor are typically modeled by a number of interacting sub-automata. The standard way of synthesizing a supervisor is to enu- merate all reachable states in the closed-loop system and then remove all states that does not fulfill the given specifications. This approach has three main problems: 1) Enumerating all reachable states in the closed-loop system is computational expensive due to the state- space explosion. 2) Typically the synthesized supervisor has a large num- ber of states and representing them as a single automa- ton will require much more memory than the memory in the hardware used to realize the supervisor. 3) While the input models to a supervisory synthesis problem typically consists of multiple automata, the output from the synthesis procedure (the supervisor) is in most cases a monolithic automaton. The rela- tion between the original modular input models and the monolithic output automaton is weak and it is troublesome for the users of such a system to really understand how the synthesis procedure restricts the input automata models. Thus, a third problem that is typically encountered for users of supervisory synthe- sis tools, e.g. [2], [3], is that they cannot manually explore the synthesis result. More specifically, the user retrieves the final supervisor for the system without any specific information regarding the events causing undesirable states. The authors in [4] propose an algorithm for manufacturing cell controllers to extract the relations between the operations defining the work in the cell from the synthesized supervisor. The main advantage of these relations is to give an easy- to-read representation of the control function and make the method usable in an industrial setting. However, not much attention is paid on how to reduce the final relational expressions for more complex systems which is the case in many industrial applications. Moreover, some restrictive conditions have been assumed for the original models, which should be satisfied in order to benefit the method. In [5], [6] an implementation of decentralized supervisory control was presented. This is performed “by embedding the control map in the plant’s local Finite State Machines and employing private sets of Boolean variables to encode the control information for each component supervisor” [6]. Although this process will assist the simplicity and clearness of the supervisors, the main focus in these papers is to solve the problem of decentralized communicating controllers. The authors in [7], [8], [9], [10], [11] have proposed another class of approaches for supervisory synthesis based on the linear algebraic representation of Petri nets model of the plants. In these methods, the specifications are added to the plants in the form of linear predicates which can be considered as constraint conditions. The resulting controller can also be formulated in a similar way as suggested in this paper. However, each approach has some restrictions. The non-blocking problem is not considered in [7]. In addition, in order to employ this approach, the system should satisfy a particular structural condition: the uncontrollable subnet extracted from the Petri net model must be loop free. In [8] the liveness problem is considered but only for controlled marked graphs. The approach proposed in [9] is applicable if the supervisory net has a convex reachability set. The focus is mainly on efficient automatic verification. In [10] the request for a maximally permissive supervisor is abandoned, in favor