Instruction-Level Test Methodology for CPU Core Self-Testing SAEED SHAMSHIRI, HADI ESMAEILZADEH, and ZAINALABDEIN NAVABI University of Tehran TIS is an instruction-level methodology for processor core self-testing that enhances instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions. Online testing can be accomplished without any performance penalty. TIS tests different parts of the processor and detects stuck-at faults. This method can be employed in offline and online testing of single-cycle, multicycle and pipelined processors. But, TIS is more appropriate for online testing of pipelined architectures in which NOP instructions are frequently executed because of data, control and structural hazards. Running test instructions instead of these NOP instructions, TIS utilizes the time that is otherwise wasted by NOPs. In this article, two different implementations of TIS are presented. One implementation employs a dedicated hardware modules for test vector generation, while the other is a software-based approach that reads test vectors from memory. These two approaches are implemented on a pipelined processor core and their area overheads are compared. To demonstrate the appropriateness of the TIS test technique, several programs are executed and fault coverage results are presented. Categories and Subject Descriptors: B.5.3 [Register-Transfer-Level Implementation]: Relia- bility and Testing—built-in tests General Terms: Verification, Design, Performance Additional Key Words and Phrases: Instruction level testing, CPU core testing, software-based self testing, test instruction set, BIST, pipelined processor 1. INTRODUCTION In many SoCs, embedded processor cores are widely used because they offer several advantages including design reuse and portability over ASICs. Core- based design allows processors to be used in a variety of applications in a cost- effective manner. On the other hand, design based on processor cores presents Authors’ address: School of Electrical and Computer Engineering, University of Tehran, North Kargar Ave., Tehran 14395-515, Iran; email: {shamshiri, hadi}@cad.ece.ut.ac.ir; navabi@ece.neu. edu. Based on “TIS: An Instruction-Level Test Methodology for CPU Core Software-Based Self-Testing” by Saeed Shamshiri, Hadi Esmaeilzadeh, and Zainalabdein Navabi, which appeared in the Pro- ceedings of the 2004 IEEE High Level Design Validation and Test Workshop (HLDVT 2004).c  2004 IEEE. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 1515 Broadway, New York, NY 10036 USA, fax: +1 (212) 869-0481, or permissions@acm.org. C  2005 ACM 1084-4309/05/1000-0673 $5.00 ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 4, October 2005, Pages 673–689.