Temperature-Insensitive Synthesis Using Multi-Vt Libraries Andrea Calimera, Enrico Macii, Massimo Poncino Dip. di Automatica e Informatica Politecnico di Torino Torino, ITALY 10129 R. Iris Bahar Division of Engineering Brown University Providence, RI, USA 02901 ABSTRACT Temperature fluctuations can alter the delay in MOS cir- cuits. However, increases in temperature do not always lead to a corresponding increase in circuit delay, specifi- cally when operating at low supply voltages. Instead a tem- perature inversion effect can be observed on the delay of MOS devices under certain conditions, where the delay ac- tually decreases as temperature increases. Given these non- monotonic effects, guaranteeing timing correctness can no longer be achieved simply by characterizing the design under worst case (i.e., high temperature) conditions. In this pa- per, we present a synthesis methodology in which multi-V th design is used to generate temperature-insensitive circuits, while minimizing leakage power dissipation as a side-effect. Our experiments with ISCAS benchmark circuits demon- strate the promise of this approach and show that significant reduction in static power is also possible. Categories and Subject Descriptors B.7 [Hardware]: Integrated Circuits General Terms Design Keywords Temperature-aware, logic synthesis, multi-threshold voltage 1. INTRODUCTION As process technology scales to increasingly smaller di- mensions, accounting for thermal effects has become increas- ingly important [10, 2]. High temperature has been shown to have a negative effect on delay, power dissipation, and re- liability of circuits. In particular, increases in on-chip tem- perature have been shown to significantly increase the delay of long wires used for buses and global interconnects [1, 11]. Short wires, on the other hand, may still be affected by tem- perature fluctuations; however, variations in delay are much smaller and since they are short and localized, they are af- fected all in the same way, so there is no gradient effect as with long wires. Finally, temperature also affects the delay and power dissipation of gates, but in different ways. Accurately modeling gate delay requires extensive charac- terization of the gates at multiple operating points. Gate de- lay has typically been characterized with three parameters: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. GLSVLSI’08, May 4–6, 2008, Orlando, Florida, USA. Copyright 2008 ACM 978-1-59593-999-9/08/05 ...$5.00. voltage, temperature, and process. In the past, delay of a cell has been characterized assuming corner values for these three parameters. For instance, ignoring process variation, a slow corner could be characterized with low voltage and high temperature and a fast corner with high voltage and low temperature. This approach has held in the past, where cells are assumed to operate at voltages around 1.2V. How- ever, when operating at low voltages (appropriate for circuits designed using 90nm technology and below), this general as- sumption does not necessarily hold, and in fact delay may decrease as temperature increases. This phenomenon is due to the fact that, at low voltages, delay is determined more by the threshold voltage, whereas with high voltages, delay is determined more by the mobility. Therefore, the delay of a gate may increase or decrease due to temperature depending largely on the value of V dd . As will be described later in the paper, there are many factors that influence this tempera- ture inversion effect in subtle ways; however, we will show that a predominant trend is that the delay of high-V th cells tends to decrease as temperature rises whereas the delay of low-V th cells tends to increase as temperature rises. This temperature inversion effect has been known for some time. However, only recently have there been works address- ing this issue, particularly for digital circuit design. For in- stance, since this phenomenon will complicate delay charac- terization for cells, one work has proposed a design method- ology based on optimizing the supply voltage to achieve temperature-variation-insensitive circuit performance [7]. For 45nm technology circuits, they propose using a supply volt- age 15%–35% higher than the nominal supply voltage in or- der to guarantee that circuit delay will not be affected by temperature variation. Another work has proposed tech- niques to bound cell and path delays accurately for static timing analysis while taking into account this inverted tem- perature effect [4]. While these previous works propose useful solutions, in this paper we focus more on the synthesis problem. That is, given this temperature inversion effect, we propose a new synthesis strategy for multi-V th circuits that will au- tomatically produce temperature-invariant designs, thereby guaranteeing that the circuit will meet specified timing con- straints for all allowable operating temperatures. We will show that our strategy also has the desirable consequence of lowering leakage power. The key to achieving reduced power is realizing that gates not on the critical path may make more aggressive use of high-V th cells when temperature in- version effects are present. This is because, the high-V th cells will decrease in delay as temperature increases, counteract- ing the effect of the increased delay with low-V th cells. The end result is a temperature-insensitive circuit that dissipates up to 41% less static power than one synthesized using a standard multi-V th synthesis approach. 5