An On-Chip Sensor to Monitor NBTI Effects in SRAMs A. Ceratti & T. Copetti & L. Bolzani & F. Vargas & R. Fagundes Received: 16 January 2013 /Accepted: 27 March 2014 /Published online: 15 April 2014 # Springer Science+Business Media New York 2014 Abstract The increasing need to store more and more infor- mation has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on- Chip (SoCs). Therefore, SRAM’ s robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-Scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which causes the memory cells aging. The main goal of this paper is to present a hardware-based approach able to monitor SRAMs’ aging during the SoC’ s lifetime based on the insertion of On- Chip Aging Sensors (OCASs). In more detail, the proposed strategy is based on the connection of one OCAS to every SRAM column, each periodically monitoring write operations on the SRAM cells. It is important to note that in order to prevent the OCAS from aging and to reduce leakage power dissipation, the OCAS circuitry is powered-off during its idle periods. The proposed hardware-based approach has been evaluated throughout SPICE simulations using 65 nm CMOS technology and the results demonstrate the sensor’ s capacity to detect early aging states and therefore, guaranteeing high SRAM reliability. To conclude, a complete analysis of the sensor’ s overheads is presented. Keywords Nano-Scale SRAM . SRAM reliability . NBTI . Aging Effect 1 Introduction In Very Deep Sub-Micron (VDSM) technology, lifetime reli- ability has become one of the key design factors to guarantee the robustness of Static Random Access Memories (SRAMs). The most critical downside of technology scaling beyond the 65 nm node is related to the non-determinism of the devices’ electrical parameters due to process variations [3, 4, 5]. This type of variation is mostly caused by random fluctuations of dopant atoms and can be observed as a fixed deviation from the device’ s nominal behaviour [5]. Indeed, time-dependent deviations in the operating characteristics of device can be observed as a type of non-ideality that results from technology scaling [2]. Essentially, two sources of time-dependent varia- tions are identified: Bias Temperature Instability (BTI), and Hot Carrier Injection (HCI) [11]. Both are physical/chemical effects that cause a degradation of the oxide and result in a drift of the threshold voltage over time. However, BTI has become the most prominent effect as it creates interface states along the whole silicon-oxide interface. Two forms of BTI can be distinguished: Negative BTI (NBTI), which affects the pMOS transistors and the dual Positive BTI (PBTI), affecting nMOS devices. It is important to note that the higher impact on technologies with silicon- based dielectrics is caused by NBTI and it consequently has become the most important reliability concern related to time- dependent degradation in SRAMs [5]. NBTI is defined as the effect that occurs when a pMOS is negatively biased and manifests itself as an increased thresh- old voltage over time. This consequently results in drive current reduction and increased noise, which in turn causes a degradation of the device’ s delay. The threshold’ s increase is estimated to be of 10–15 % per year, depending on the targeted technology and its environment, while with a smaller magnitude though, the delay degradation follows the same trend [5]. According to [8], a threshold’ s variation of about Responsible Editor: V. Champac A. Ceratti : T. Copetti : L. Bolzani (*) : F. Vargas Catholic University of Rio Grande do Sul – PUCRS, School of Engineering, Porto, Alegre, Brazil e-mail: leticiabolzani@gmail.com J Electron Test (2014) 30:159–169 DOI 10.1007/s10836-014-5444-x