RAISE: A Detailed Routing Algorithm for Field-Programmable Gate Arrays V. Baena-Lecuyer, M. A. Aguirre, A. Torralba, L. G. Franquelo and J. Faura* Dpto. de Ingenier´ ıa Electr ´ onica Escuela Superior de Ingenieros, Avda. Reina Mercedes s/n, Sevilla–41012(SPAIN) Tel.: +34 (9)5 455 68 57 FAX: +34 (9)5 455 68 49 e–mail: baena@gte.esi.us.es *SIDSA C/ Isaac Newton 1, Parque Tecnol ´ ogico de Madrid, Tres Cantos, Madrid–28760 Tel.: +34 (9)1 803 50 52 e–mail: faura@sidsa.es Conference Topic: FPGA Design and Applications Abstract— This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP- GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelentrouting results have been obtainedover a set of several benchmark circuits getting solutions close to the minimum number of tracks. I. INTRODUCTION In the last years, the use of Field-Programmable Gate Arrays (FPGAs) has been widely accepted as an attractive means of implementing digital cir- cuits. There is a wide range of comercial FPGAs, but one of the most important types is the symmet- rical FPGA, which consists of rows and columns of logic blocks with horizontal routing channels be- tween rows and vertical routing channel between columns. This type of FPGAs was first introduced by Xilinx in 1986, but currently it can be found in some of the Altera and Quicklogic families. Symmetrical FPGAs can reach very high logic ca- pacities; for this reason, a key problem in the de- sign of this kind of FPGAs is the structure of their routing channels. The use of short segments im- prove chip area (less segment length is wasted us- ing short segments) but to provide long connec- tions, the interconnection of short segments via programmable routing switches is required, re- ducing speed performance. On the other hand, the uses of long segments wastes chip area but im- proves speed performance (less segments are re- quired to make long connections passing through only a few switches). This tradeoff forces the design of complex rout- ing channels, with different lenght segments, which requires sofisticated Computer Aided De- sign (CAD) Tools. Five stages are usually involved in mapping a cir- cuit: design entry, logic optimization technology mapping, placement and routing. The last one is made in two step: global routing and detailed rout- ing. This paper presents RAISE, a new detailed router adapted for generic symmetrical FPGAs. II. RAISE: ROUTER USING ADAPTIVE SIMULATED EVOLU- TION RAISE is based on SILK [3], a simulated evolu- tion program for channel routing. Before running RAISE, for each point to point net, a set of pos- sible paths is generated (for example, using the technique called Coarse Graph Expansion (CGE) [1] [2]). RAISE takes this set and searches for a path subset that make possible the routing of all the nets, while minimizing the delays. Theese steps are carried out by RAISE: 1. Initial Routing. 2. Rip-Up and Rerouting. 3. Postoptimization. A. Initial Routing The algorithm, of statistical nature, needs a seed to start the iterative process. This seed or solution, does not need to be feasible, that is, it can have conflicts, which have to be solved in the following steps. Our detailed router takes for each point to point net the path with minimum delay. The delay can be calculated with the RC-Tree algorithm of [4]. 1