RESIDUAL STRESS IN SILICON CAUSED BY CU-SN WAFER-LEVEL PACKAGING Maaike M.V. Taklo SINTEF Oslo, Norway Astrid-Sofie Vardøy SINTEF Oslo, Norway Ingrid De Wolf IMEC, KU Leuven Leuven, Belgium Veerle Simons IMEC Leuven, Belgium H.J. van de Wiel TNO Eindhoven, The Netherlands Adri van der Waal TNO Eindhoven, The Netherlands Adriana Lapadatu Sensonor Horten, Norway Stian Martinsen Sensonor Horten, Norway Bernhard Wunderle TUC Chemnitz, Germany ABSTRACT The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high- performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro- Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device. INTRODUCTION The use of copper (Cu) in microelectronics and for micro electromechanical systems (MEMS) has expanded as the prices of silver and gold lately have increased significantly. Cu is widely applied in advanced packaging as a fill material in through silicon vias (TSVs) [1], as bump material for fine pitch interconnects [1], and is gradually also more used as a wafer bonding material to hermetically seal MEMS [2]. Wafer level packaging enables reduction of final device sizes, simplicity of handling during final assembly and resultantly cost efficiency of a large variety of MEMS in high volume production. Cu-Sn 1 Copyright © 2013 by ASME Proceedings of the ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems InterPACK2013 July 16-18, 2013, Burlingame, CA, USA IPACK2013-73317