2690 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 10, OCTOBER 2007 A Reliable Metric for Mobility Extraction of Short-Channel MOSFETs Simone Severi, Luigi Pantisano, Emmanuel Augendre, Enrique San Andrés, Pierre Eyben, and Kristin De Meyer Abstract—When comparing the extracted carrier mobility of long- and short-channel transistors, special consideration must be given to the metallurgical gate length (L met ), neglecting the im- pact of source and drain junction profiles. L met can be identified with nanometer precision by using RF split-C –V measurements, and physical and electrical analysis can demonstrate the accu- racy of the method. Another important parameter, the external transistor resistance (R sd ), can be identified with linear current measurements of short-channel devices. However, it is important to quantify the mobility dependence from the gate length in order to obtain an accurate result. A method to estimate the electrical field (E eff ) of short-channel devices is proposed. The extracted short-channel mobility shows a universal behavior identical to the classical long-channel one. Index Terms—Length and resistance measurements, MOSFET, scattering. I. INTRODUCTION T HE EXTRACTION of basic MOSFET parameters like the effective channel length (L eff ), the source/drain (S/D) resistance (R sd ) and the mobility of short-channel devices is of fundamental importance for the analysis of advanced CMOS technologies. In particular, this is the case for strain-Si materials, ultrashallow junction and high-k dielectrics applica- tions. The latest can induce mobility variations between long- and short-channel devices attributed to the different dielectric exposure to an oxygen rich/poor environment. Several methods have been developed in the past to deter- mine with fair accuracy both L eff and R sd . The difficulty lies in the fact that these two parameters are correlated. When extraction techniques based on the linear drain currents are considered, generally, L eff and R sd are considered weakly V g dependent. The so-called L array methods [1], [2] are unstable if a large range of gate lengths is considered and lead to high uncertainties of the extracted values. However, more recently, these methods have been successfully used both for modeling Manuscript received October 18, 2006; revised May 29, 2007. The review of this paper was arranged by Editor S. Kimura. S. Severi, L. Pantisano, and P. Eyben, and K. De Meyer are with the Interuniversity Microelectronics Center (IMEC), 3000 Leuven, Belgium. E. Augendre is with Laboratoire d’Electronique et de Technologies de l’Information du Commissariat à l’Energie Atomique (LETI-CEA), 38054 Grenoble, France. E. San Andrés is with Universidad Complutense de Madrid (UCM), 28040 Madrid, Spain. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2007.904011 [9] and characterization of short-channel-strained Si devices [10]. The use of a limited range of sub-100-nm gate-length tran- sistors can greatly improve the extraction linearity. Techniques such as the simple or modified shift and ratio methods [3], [4] increase resolution and robustness. However, these methods are expected to have accuracy not lower than 15 nm, not enough for devices in the sub-100-nm range. All of these methods assume a gate-length-independent mobility model which, in general, is not verified for current technologies which use pocket implants. This prevents an accurate extraction of L eff and R sd . Capacitance measurement techniques allow gate-length ex- traction without including any transistor conduction mecha- nisms [5], [6]. Split inversion capacitance measurements [14] of short-channel devices are usually considered, but the lack of understanding on C ov , in particular of the inner (C if ) and parallel plate (C pp ) components, has prevented accurate L eff extractions in sub-100-nm devices [7], [8]. Furthermore, with the scaling of the physical oxide thickness and the increase in gate leakage, the use of conventional split-C–V measurements could lead to capacitance distortion and extraction inaccuracies. In this paper, L eff is extracted using the novel RF-split-C–V method [11] and correctly taking into account the parasitic overlap contribution at flatband voltage V fb [15]. Scanning spreading resistance measurements (SSRMs) and extensive statistical analysis verify the consistency of the extraction. In pockets implant technologies, R sd is overestimated by com- monly used techniques due to the variation of mobility with the gate length. We indicate with extensive measurements the possibility to find more realistic values by measuring small channel transistors at high effective fields. After L eff and R sd , the mobility of short-channel devices is studied and the poten- tial error attributed to measurements or extraction inaccuracies is quantified. Finally, in the same spirit of Takagi’s model, an effective field concept for short-channel devices is proposed. II. EXPERIMENT CMOS wafers processed with a shallow trench isolation module were considered. The equivalent oxide thickness of SiON (14% N) dielectric ranged between 1.5 and 2 nm. Poly-Si was considered as gate electrode. For nMOS, the poly-Si was predoped with phosphorous (P) and annealed prior gate etch, while for pMOS, boron (B) was incorporated during the highly doped drain (HDD) junctions implantation. Lowly doped drain (LDD) and pocket implants were consid- ered for both nMOS [arsenic (As) 1 keV 7 × 10 14 cm -2 and B 5 keV 5.5 × 10 13 cm -2 , respectively] and pMOS (B 0.5 keV 7 × 10 14 cm -2 and As 40 keV 3.5 × 10 13 cm -2 , respectively). 0018-9383/$25.00 © 2007 IEEE