IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. xx, No. xx, February 2010. 1 Abstract— On-chip monitoring of environmental information, such as temperature, voltage, and error data, is becoming increasingly important. To address this need, a low-overhead architectural approach to monitor data collection and use in multicore systems is described. A key aspect of our stand-alone monitoring subsystem is a low-complexity, on-chip network designed to transport monitor data with multiple priority levels. Collected monitor information is evaluated by a dedicated processor. Experimental results using architectural and interconnect simulators show that the new low-overhead subsystem facilitates employment of thermal and delay-aware dynamic voltage and frequency scaling. In contrast to using existing on-chip interconnect resources to communicate monitor data, the new subsystem provides necessary bandwidth for monitor data traffic without impacting application data traffic. Synthesis results show that our dedicated monitoring approach consumes about 0.2% of multicore area and power resources for an 8-core system based on AMD Athlon 64 processor cores. Index Terms—Network on chip, on-chip monitoring, multicore. I. INTRODUCTION omputing in the presence of various sources of uncertainty significantly complicates the design and implementation task. Multicore and manycore systems present a particular challenge as large numbers of processor cores are integrated into single-chip platforms. As multicore deployments become more diverse, a static system operating environment can no longer be assumed. These systems are susceptible to a number of reliability, performance, and power constraints that must be carefully addressed during system operation. As the size of multicore systems increase, the importance of using run-time monitoring information to tune system operation becomes critical. Fault tolerance issues are particularly acute for multicore system design in which system elements, such as caches and memory controllers, are Manuscript received August 4, 2009; revised February 2, 2010. This work was supported by the Semiconductor Research Corporation under Task 1595.001. J. Zhao, W. Burleson and R. Tessier are with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 USA. (e-mail: tessier@ecs.umass.edu). S. Madduri is with Intel Corporation, Hillsboro, OR 97123 USA. R. Vadlamani is with Qualcomm Inc., Boxborough, MA 01719 USA. Digital Object Identifier xxxx. shared by many individual cores. Recent multicore processors from Intel (Montecito), AMD (Opteron) and IBM (Cell) use on-chip monitors for run-time estimates of temperature, power, clock jitter, supply noise and performance for a small number of cores. However, an automated, dedicated approach to the collection and use of monitor data in multicores has not been developed. Multicore monitor information represents a substantial data workload that must be analyzed in its own right, separate from the core processing capabilities of the multicore system. This information can then be used to configure multicore resources in conjunction with system and application software. System critical monitor information, including soft error failures, wear-out data, and voltage droop often require immediate attention at the system level. As demonstrated in this manuscript, the presence of a fast and dedicated, but minimal, interconnect for monitor information allows for effective, dedicated monitor data transfer. Monitor information from multiple multicore monitors is then assessed in real time at one or more processing components. The results of this processing are then used to affect multicore behavior via operations such as per-core frequency and voltage scaling, among others. The dedicated collection and processing of system-on-chip (SoC) environmental information from on-chip monitors provides an important multicore architecture design dimension. This research presents an integrated approach to address this issue with the development of a complete monitor subsystem for SoCs, including on-chip monitors, a low-overhead on-chip interconnect, which is optimized for monitors, and one or more monitor data processing components. The interconnect has been designed to provide interfaces to a variety of different monitor types and monitor data processing components, from low-complexity thermal monitors to a microcontroller. Although simplified versus typical on-chip interconnects, the monitor network-on-chip's (MNoC) support for irregular topologies, priority-based data transfer, and dead-lock free routing provide a flexible data collection environment. Following monitor data processing, MNoC is used as an interface to control circuitry (e.g. dynamic voltage and frequency scaling (DVFS) control) which affects multicore operation. The overhead and performance benefit of our monitoring A Dedicated Monitoring Infrastructure For Multicore Processors Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Senior Member IEEE, and Russell Tessier, Senior Member IEEE C