Discrete Wavelet Transform FPGA Design using MatLab/Simulink Uwe Meyer-Baese a , A. Vera b , A. Meyer-Baese a , M. Pattichis b , R. Perry a , a FAMU-FSU, ECE Dept., 2525 Pottsdamer Street, Tallahassee, FL USA-32310; b University of New Mexico, ECE Dept., Albuquerque, NM 87131 ABSTRACT Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of the engineering skills ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink based design flow. This not only allows the over 1 million MatLab users to design FPGAs but also to by-pass the hardware design engineer leading to a significant reduction in development time. Critical however with this design flow are: (1) quality-of-results, (2) sophistication of Simulink block library, (3) compile time, (4) cost and availability of development boards, and (5) cost, functionality, and ease-of-use of the FPGA vendor provided design tools. Keywords: FPGA, two channel filter bank and Wavelet, Simulink, top down design flow 1. INTRODUCTION Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, multi channel filter banks, or wavelets, to name just a few, previously built with ASICs or programmable digital signal processors, are now most often replaced by FPGAs. The two FPGA market leaders (Altera and Xilinx) both report revenues greater than $1 billion. FPGAs have enjoyed steady growth of more than 20% in the last decade, outperforming ASICs and programmable digital signal processors (PDSPs) by 10%. 2. DESIGN CHALLENGE System-C 1 , Handel-C 2 , X-Blox 3-5 or other high level tools have tried in the past to close the gap between system level design and physical FPGA implementation. However, the acceptance of these design tools has not been very favorable and they have become niche products 1-2 mainly for configurable processor design rather than as a main stream application tool, like VHDL or Verilog compiler tools on the lower implementation level. Another approach, now favored by both Xilinx 5 and Altera 6 is the design using MatLab/Simulink interface. The reason this approach is more successful is the large base of MatLab programmers of over 1 million world wide 5,6 . This design flow has several other advantages, as for instance • Many high end FPGA applications today are in the DSP field, where MatLab/Simulink is the preferred simulation tool anyway. • MatLab/Simulink has many state-of-the art algorithms implemented in over 25 MatLab and Simulink toolboxes, see Figs. 1 and 2. • Simulation in Simulink can be bit precise and is an ideal framework to generate testbenches. • The FPGA vendor provided toolboxes allow a concentration on the algorithm implementation, rather than the design tool optimizations. The question when using such a relatively new MatLab/Simulink design flow for a designer however is the question, if this flow delivers good quality of results (QoR), or if the synthesized designs are more of a “quick and dirty” quality. Experience in the past with tools like X-Blox 3-5 showed that on average ca. 20% higher area could be expected using a