II-117 ECCTD’01 - European Conference on Circuit Theory and Design, August 28-31, 2001, Espoo, Finland Performance Estimation in Analog Computer Aided Design I. Faik Baskaya* and Günhan Dündar* Abstract – In this paper, part of a joint effort in developing an analog design automation system with different levels of synthesis has been described. The study has been restricted to various types of analog CMOS circuits. Transistors have been modelled using analog neural networks trained with data obtained from simulation tools. Using these models in a circuit block, DC operating points have been determined iteratively and power dissipated by the circuit has been calculated in the DC analysis. In the AC analysis, gain and bandwidth of the system have been calculated, completing an evaluation cycle. Evaluation cycles have been used in a search mechanism where a range of input parameters have been swept in order to obtain the performance limits of the given circuit topology. 1 Introduction Automation in analog design is attracting increased interest because of the large amount of time and effort spent in manual design. As an efficient strategy for automation, hierarchical decomposition, which helps dividing the complete design task into sub-tasks may be proposed [1]. Typically at the top of the flow, system level synthesis, governed by system specifications, which decide the architecture to be used, takes place. Next level can be called circuit level synthesis, as it will be dealing with optimization of circuit blocks used in the macro-models of the higher level, taking device model parameters into account. Finally, at the lowest level will be layout synthesis, in order to give out the physical realization of the circuit incorporating process and fabrication data [2-4]. If; however, the circuit level synthesizer can not find a possible solution to the optimization problem of a certain circuit block demanded by higher level synthesizer; i.e., such a circuit is not possible, some changes will have to be made in the architecture, thus nullifying all the efforts at the circuit optimization level. In order to overcome such a problem, either the output parameters of the circuit have to be expressed in terms of each other so that a decision can be made analytically or a region has to be searched by sweeping the input parameters and evaluating their respective outputs. Since the analytical method is a tough one and the performance evaluators being used in many circuit optimizers are very slow for such a mission, an approximate albeit faster estimation of the performance would be helpful in order to search whether a desired solution exists in a certain region prior to further optimization efforts. In this work, an approximate performance estimation tool for only four of the performance specifications; namely, gain, bandwidth, power consumption, and layout area of an analog block will be described. High accuracy is not demanded; however, high speed is a must. Using such a high- speed estimation, checking a large design space in an acceptable time will be possible in order to determine performance limits of the relevant circuit block. To this end, a fast performance estimator was developed to be used for generating circuit performance ranges. The estimator utilizes neural networks and/or equations to model the DC behavior and small signal parameters of transistors, an iterative methodology for estimating DC operating conditions, and an equation based approach for estimating AC performance parameters in an evaluation cycle. This estimator is run for many input values swept in a user-determined range to generate a data set from which circuit level performance limitations can be deduced. The overall system is depicted in Figure 1. Figure 1: Flowchart of the performance estimation and design space exploration system. In the next section, neural network based MOSFET modeling has been described. Sections 3 and 4 discuss the DC and AC analysis steps of the evaluation cycle. Section 5 explains search mechanism of the system. Section 6 concludes the paper. Finished? Initialization Read Neural Network Models, Block Library and Circuit Data Start Evaluation Obtain valid results New inputs N End Y *Bogaziçi University, Department of Electrical and Electronic Engineering, Bebek 80815, Istanbul, Turkey, e-mail:dundar@boun.edu.tr , Tel: +90 (212) 263 1540 ext 1860, Fax: +90 (212) 287 2465