TABSH: Tag-Based Stochastic Hardware Sarah Abdallah Ali Chehab Ayman Kayssi Imad H. Elhajj Department of Electrical and Computer Engineering American University of Beirut Beirut 1107 2020, Lebanon {saa78, chehab, ayman, imad.elhajj}@aub.edu.lb Abstract— Many popular and emerging applications are error tolerant by nature: their operations are considered “correct” even if the underlying hardware, to a certain extent, is erroneous. Under these circumstances, fault-correction mechanisms turn out to be unnecessary. This gave birth to “stochastic processors” that are under-designed and allow results not to be fully correct. Relaxing the hardware correctness requirements as a way to reduce energy consumption is a major trend first because of the emergence of green electronics and second the boom in portable devices with limited battery capacity. In this paper, we present TABSH, a SIMD Tag-Based Stochastic Hardware, and we compare its energy figures to a SISD processor, and show up to 65% energy saving per instruction. I. INTRODUCTION Energy-efficient computing has gained major focus recently such that energy consumption became the most essential interest of today’s hardware designers. Moreover, the move towards green computing has become indispensable from both environmental and financial aspects. At the same time, many emerging applications are classified as recognition, mining, and synthesis (RMS) applications and stream-based media applications. Research in this area made use of the error lenience of RMS applications in order to relax the zero-error tolerance requirement at the hardware level as well as to migrate error correction or concealment to the software level. The main advantage is the major power savings that are obtained once hardware errors are tolerated, since the circuits can be operated using reduced power supply levels. Hardware errors are thus allowed by the application at minimal additional overhead, but at a big improvement in energy consumption. In this paper we propose an energy efficient stochastic processor that takes advantage of two characteristics of RMS and multimedia applications: error tolerance and parallelization. In fact, many of these applications can be parallelized as Single-Instruction-Multiple-Data (SIMD), which allows for great energy savings based on our proposed design. Our simulated stochastic processor provides up to 65% energy saving per instruction. The paper is organized as follows: we start by introducing error-tolerant applications in section II and we present the different stochastic architectures in section III. Then, we propose our Tag-Based Stochastic Hardware (TABSH) in section IV. Implementation and results are described in sections V and VI, respectively, and we conclude in section VII. II. ERROR-TOLERANT APPLICATIONS Most of the techniques proposed previously focus on error correction. However, the applications of interest (RMS and media applications) are characterized by high error tolerance. Accordingly, we can embrace errors instead of correcting them, and hence the extra software and hardware overhead for the correction mechanisms can be avoided, leading to substantial energy savings. Much research in the literature was conducted on these applications, their type, characteristics, and how they behave when subjected to hardware uncertainties. Li and Yeung conducted in [10] a study to quantify the error tolerance of applications as compared to that of the architecture. A program is considered correct if it yields results that are acceptable to the user. Such applications are referred to as soft-output applications; these include artificial intelligence, decision-making applications, and multimedia programs among others. Thaker et al. exploit another characteristic of error-tolerant applications in [11], by separating data and control blocks. The study shows that errors can be tolerated only in certain sections of the application code, namely the data sections. Control sections however are essential to the correct functionality of the application and cannot tolerate errors. A compiler technique is presented to tag control instructions that need to be protected. Sundaram et al. extended in [12] the research in [11] and they proposed methods to protect control instructions, notably by replicating them. While this method is better than full replication of code, it still produces overhead which might not be desirable, especially if the application is not data intensive, and has large control blocks. Lin et al. used redundancy at the hardware level to provide error resiliency [13]. The Selectively Fortified Computing (SFC) approach is application-specific; it identifies the portions of the system that are vulnerable and protects them with hardware redundancy. However, the main objective of SFC is to provide resilience to errors and high results accuracy, not energy efficiency. III. STOCHASTIC ARCHITECTURES Results from previous work show the importance of separating data and control blocks, and protecting the latter. Instruction replication is deemed inefficient because of the code size overhead. Also, while hardware redundancy provides improved accuracy, and even though the power consumption 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC) 978-1-4799-2543-8/13/$31.00 ©2013 IEEE 115