CONCURRENCY AND COMPUTATION: PRACTICE AND EXPERIENCE Concurrency Computat.: Pract. Exper. (2012) Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cpe.2975 SPECIAL ISSUE PAPER Finding near-perfect parameters for hardware and code optimizations with automatic multi-objective design space explorations Ralf Jahr 1, * ,† , Horia Calborean 2 , Lucian Vintan 2 and Theo Ungerer 1 1 Department of Computer Science, University of Augsburg, 85135 Augsburg, Germany 2 “Lucian Blaga” University of Sibiu, Computer Science & Engineering Department, E. Cioran Str., No. 4, Sibiu - 550025, Romania SUMMARY In the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before produc- tion, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objec- tive that needs to be optimized; power consumption, area, and so on have become very important. Thus, the best configurations have to be found in respect to multiple objectives. In this article, we use a multi-objective design space exploration tool called Framework for Automatic Design Space Exploration (FADSE) to auto- matically find near-optimal configurations in the vast design space of a processor architecture together with a tool for code optimizations and hence evaluate both automatically. As example, we use the Grid ALU Pro- cessor (GAP) and its postlink optimizer called GAPtimize, which can apply feedback-directed and platform- specific code optimizations. Our results show that FADSE is able to cope with both design spaces. Less than 25% of the maximal reasonable hardware effort for the scalable elements of the GAP is enough to achieve the processor’s performance maximum. With a performance reduction tolerance of 10%, the necessary hardware complexity can be further reduced by about two-thirds. The found high-quality configurations are analyzed, exhibiting strong relationships between the parameters of the GAP, the distribution of complexity, and the total performance. These performance numbers can be improved by applying code optimizations concur- rently to optimizing the hardware parameters. FADSE can find near-optimal configurations by effectively combining and selecting parameters for hardware and code optimizations in a short time. The maximum observed speedup is 15%. With the use of code optimizations, the maximum possible reduction of the hardware resources, while sustaining the same performance level, is 50%. Copyright © 2012 John Wiley & Sons, Ltd. Received 20 December 2011; Revised 10 October 2012; Accepted 5 November 2012 KEY WORDS: automatic design space exploration; multi-objective optimization; hardware complexity estimation; code optimization 1. INTRODUCTION As in the last decade, the complexity of novel processor architectures is going to increase in the future. This is caused by the steadily growing number of transistors. Although for early processor architectures the available number of transistors was a limiting bound, the architectures proposed more recently have the freedom to use lots of hardware. To cope with the increasing complexity of designs, while preserving effective usage of hardware resources, is one of the challenges to be solved by new approaches. *Correspondence to: Ralf Jahr, Department of Computer Science, University of Augsburg, 85135 Augsburg, Germany. † E-mail: jahr@informatik.uni-augsburg.de Copyright © 2012 John Wiley & Sons, Ltd.