Compact model for short channel symmetric doped double-gate MOSFETs Antonio Cerdeira a, * , Benjamín Iñiguez b , Magali Estrada a a Sección de Electrónica del Estado Sólido, Departamento de Ingeniería Eléctrica, CINVESTAV, D.F., Mexico b Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, Tarragona, Spain article info Article history: Received 21 September 2007 Received in revised form 18 February 2008 Accepted 15 March 2008 Available online 28 April 2008 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Compact modeling Doped double-gate MOSFET Double-gate current modeling Short channel effects abstract A new compact model for currents in short channel symmetric double-gate MOSFETs is presented which considers a doped silicon layer in the range of concentrations between 10 14 and 3  10 18 cm 3 . The mobile charge density is calculated using analytical expressions obtained from modeling the surface potential and the difference of potentials at the surface and at the center of the Si doped layer without the need to solve any transcendental equations. Analytical expressions for the current–voltage characteristics are presented, as function of silicon layer impurity concentration, gate dielectric and silicon layer thickness, including var- iable mobility. The short channel effects included are velocity saturation, DIBL, V T roll-off, channel length shortening and series resistance. Comparison of modeled with simulated characteristics obtained in ATLAS device simulator for the transfer characteristics in linear and saturation regions, as well for as output char- acteristics, show good agreement within the practical range of gate and drain voltages, as well as gate dielectric and silicon layer thicknesses. The model can be easily introduced in circuit simulators. Ó 2008 Elsevier Ltd. All rights reserved. 1. Introduction It is well known the advantages of silicon-on-insulator (SOI) MOSFETs over bulk transistors related to reduced short channel ef- fects, lower parasitic capacitances and increased circuit speed. These features make them very attractive for applications in low power and low voltage digital and analog integrated circuits [1]. Among SOI devices, double-gate (DG) transistors are also consid- ered a very attractive option due to the improvement of the perfor- mance in the sub-50 nm gate length [2], because of the stronger control of the channel by the gate compared to the simple gate tran- sistor. The drain-induced barrier lowering, the threshold voltage roll- off and the off-state leakage can also be significantly reduced [3]. Because of the above mentioned features, DG MOSFETs devices are especially important for analog and mixed circuit applications, making the development of accurate and CAD compatible compact models a really urgent task. Up to know the main problem for modeling fully depleted DG devices has been that the potential at the surface and the potential at the middle of the silicon layer are related and can not be treated independently one from the other. In addition, the electric field and gate voltage of the device as function of these potentials are ex- pressed by transcendental equations that have no analytical solu- tion. An analytical solution can be obtained in the case of undoped silicon layer. A review of undoped models for long channel devices was presented in [4] and the introduction of short channel effects for undoped devices down to 50 nm was done in [5]. The case of highly-doped silicon layer was also presented in [6] where some approximations lead to a constant value for the differ- ence of potentials. In [7] we presented an analytical expression that models the variation of surface potential as well as the differ- ence of potential at the surface and at the middle of the silicon layer as a function of silicon layer impurity concentration, gate dielectric and silicon layer thickness, for the typical range of ap- plied voltages. The expression obtained was first used to derive an analytical continuous compact model with variable mobility, for the current–voltage characteristics of long channel symmetric DG MOSFETs which, for the first time, considered doped silicon layer in the range of 10 14 cm 3 to 3  10 18 cm 3 . This core model was later complemented including short chan- nel effects, but only for the case of constant mobility [8,9]. In this paper we use the analytical expressions presented in [7] to derive a compact model for doped symmetric DG MOSFETs with variable mobility that takes into account short channel effects (SCE), as velocity saturation, DIBL, V T roll-off, channel length short- ening and series resistance. In order to validate the model, calculated currents are compared with simulated using 2D simulation in ATLAS [10]. 2. DG MOSFET structure The double-gate transistor structure under analysis is shown in Fig. 1, where Na is the uniform acceptor concentration in the 0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.03.009 * Corresponding author. Tel.: +52 55 5747 3780; fax: +52 55 5747 3978. E-mail address: cerdeira@cinvestav.mx (A. Cerdeira). Solid-State Electronics 52 (2008) 1064–1070 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse