1-4244-1323-0/07/$25.00 2007 IEEE 120 2007 9th Electronics Packaging Technology Conference Lithography for Patterning inside through-Si Vias Nga P. Pham, Deniz S. Tezcan, Bivragh Majeed , Piet De Moor, Kris Baert, Bart Swinnen and Wouter Ruythooren IMEC vzw Kapeldreef 75, B-3001 Leuven, Belgium Email: pham@imec.be , Tel: + 32 16 28 7690 Abstract Lithographic patterning inside through Si vias (TSV) requires conformal coating of resist over high topography and exposure with a large gap distance. This paper investigates some parameters that have an effect on the resist pattern definition at the bottom of ~100µm deep via. The influences of the large gap exposure, resist thickness and resist type to the dimension of resist patterns have been studied. The relation of resist thickness to the size of the Si vias is also reported. Finally, an example of patterned resist inside via as a masking layer for dielectric patterning is presented as well. Introduction Through silicon via (TSV) technology is an enabling technology for three-dimensional (3D) wafer packaging. One of the TSV technology developments that is currently ongoing at IMEC is the post-CMOS TSV process for 3D wafer level packaging (WLP). The process is applied at the backside of a finished CMOS wafer, thus making it more independent from the process on wafer frontside and can be used for wafers from different technologies. The TSV process starts with the thinning of a wafer to a thickness of ~100µm on a carrier followed by the dry etching, passivation and metallization of the via. Details of the process can be found elsewhere [1]. Fig 1 is a schematic drawing of a post-CMOS TSV process flow, which describes the 3 main steps of the process: via formation, dielectric patterning and metallization. One of the challenging steps in this process is to pattern the dielectric layer at the bottom of a 100µm-deep via (Fig 1b). A spray coated photoresist layer has been used as a masking layer for the patterning of this dielectric layer. Two main requirements for this step are the conformal coating of the resist layer over the high topography surface and the lithographic process for resist pattern definition at the bottom of the via. A process to obtain conformal coating of resist and to pattern the feature at a high topography (~100µm deep) has been presented earlier [2]. Although some results on patterning the spray coated [2,3] or electroplated resist [4] over high topography have been reported, a study on the influence of the lithography on the patterned features is still lacking. In this paper, we investigate the influence of the exposure gap and the resist thickness on the resist pattern definition. The dependence of resist thickness at the bottom of the via on the via size is also studied. Because the resist is used as a masking layer for dielectric patterning, it is very important to understand the impact of different process parameters to the pattern size. 1. Wafer preparation In order to investigate the influence of the lithographic process to the resist pattern definition, both 200mm flat Si wafers and wafers with etched via were prepared. The wafers were coated with positive photoresist AZ4562. For conformal coating of the resist layer over wafers with deep-etched via, the resist was spray coated using an EVG 101 system [2]. The alignment was performed on an EVG IQ aligner using a broadband exposure for AZ4562 resist. After exposure, the resist patterns were developed in a potassium based developer solution. 2. Large gap exposure In all the reported cases, contact printing was used to pattern the features at the bottom of a deep-etched via or trench [1-4]. For lithography on a planar surface, when hard contact mode is applied, the gap between mask and the resist surface is zero (Fig 2a). In the case of patterning at the bottom of the via, the gap between the mask and the resist surface is basically equal to the depth of the via (Fig 1b). So the resist layer at the bottom of the via is actually exposed with proximity mode (Fig 2b). The gap typically causes a diffraction of the exposure light through the feature on the mask. That result in the enlargement (for positive resist) or reduction (for negative resist) of the top diameter of the resist pattern compared to the feature on the mask. The effect is called the loss of resolution. This loss of resolution is related by the minimum line width (l m ) that can be printed [5] (in case of exposure a pair of line with equal width l and spacing l ) : 2 / 1 ) ( z k l m λ ≅ (1) where k is a constant, which is a process-related factor, λ is the wavelength of the exposure radiation and z is the gap between the mask and resist surface. Therefore it is essential to understand the loss of resolution in order to figure out the actual size of the pattern on the wafer surface. As described in the formula, loss of resolution can not be avoided but it can be improved by the process related factor k. This formula describes a simple relation of the loss of resolution to the exposure gap but it does not include the resist layer. In this section we will focus on the experiment using large gap exposure to see the influence of the exposure gap to the resist feature size. To investigate the pattern size at the bottom of the via, we simulate the exposure on a flat wafer with the exposure gap equal to the depth of a via. A 120µm proximity exposure mode (120µm exposure gap between mask and wafer’s surface) was applied on a flat wafer (Fig 2b). The proximity gap of 120µm was used to simulate a worst case condition where an uneven resist thickness caused by spray coating may increase the gap beyond the nominal via depth.