ISDRS 2007, December 12-14, 2007, College Park, MD, USA ISDRS 2007 – http://www.ece.umd.edu/ISDRS Simplified Si Resonant Interband Tunnel Diodes Phillip E. Thompson a , Glenn G. Jernigan a , Si-Young Park, b Ronghua Yu, c R. Anisha, b Paul R. Berger b,c , David Pawlik d , Raymond Krom d , and Sean L. Rommel d a Code 6812, Naval Research Laboratory Washington, DC, 20375 USA, phillip.thompson@nrl.navy.mil, b Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210 USA c Department of Physics, The Ohio State University, Columbus, OH 43210 USA d Microelectronic Engineering Department, Rochester Institute of Technology, Rochester, NY 14623 USA A driving force in electronic device research has been increased functionality with reduced energy loss. One of the techniques proposed for meeting these goals has been the employment of tunnel diodes integrated with conventional transistors to form logic and memory circuits. Considerable progress has been made in the area of Si-based resonant interband tunnel diodes (RITD). Discrete RITDs have been reported that have a peak-to-valley current ratio (PVCR) greater than 6 [1], a peak current density (PCD) greater than 218 kA/cm 2 [2], and a voltage swing, V s , greater than 560 mV[3]. All of these devices, made by different research groups, have features in common: a) The electron tunneling occurs between bound states in the valence band and the conduction band created by highly doped layers formed by delta doping; b) a spacer layer between the two delta-doped layers which includes Si 1-x Ge x to reduce the bandgap and reduce the diffusion of dopants from the p-delta-doped layer; c) epitaxial growth at low temperature to reduce both the diffusion of dopants and the segregation of constituents during the growth; and d) a post-growth anneal to reduce the effect of point defects which occur due to the low temperature growth. In particular, the room temperature RITD performance has been shown to be sensitive to the Ge concentration [4], width of the alloy layer [5] and to the temperature of the post-growth anneal [4]. In spite of the narrow process windows, SiGe RITDs have been successfully integrated with both complementary metal oxide semiconductor (CMOS) transistors [6] and heterojunction bipolar transistors (HBT) [7] to form elementary logic circuits. In this abstract, Si RITDs are designed and fabricated so that neither a Ge alloy layer, nor a post-growth anneal, is required to obtain a Si tunnel diode suitable for integration. In addition the thermal stability of the Si-RITDs are investigated in the temperature interval 500 o C to 675 o C, since the devices may be exposed to these temperatures during an integrated circuit process, such as the formation of ohmic contacts. Two device structures were investigated, Fig. 1. As noted in the figure, there are many common features including substrate type, growth initiated at 650 o C prior to growth of the buffer layer, B as the p-type dopant and P as the n-type dopant, 320 o C substrate temperature for the low temperature epitaxial growth, delta doping concentrations, and 6 nm spacer width. The elements differentiating the structures occur after the deposition of the P δ-doped layer. In structure “A” the substrate growth temperature is maintained at 320 o C to minimize the P segregation and B diffusion and the top contact layer is comprised of three P δ-doped layers separated by 2.5 nm n + Si followed by a 17.5 nm n + Si layer to minimize the series resistance at the top contact. In structure “B” the substrate growth temperature is maintained at 320 o C to grow 5nm undoped Si to trap the segregating P. Then the substrate temperature is raised to 550 o C (without growth) and 70 nm of undoped Si is grown, exploiting the fact that the surface segregation of the P has increased by more than an order of magnitude, Fig. 2, and sweeps the excess P to the surface, effectively sharpening the P delta layer and providing a low resistance surface contact layer. Devices were fabricated using standard lithographic techniques. Ti/Au dots formed the front contact along with a Ti/Au backside contact. The RITDs were mesa isolated. The current-voltage (I-V) characteristics of the as-grown RITD are presented in Fig. 3, where it is shown that both structures have a PVCR in excess of 2 and a PCD around 1 kA/cm 2 . The anneal characteristics of the RITD are shown in Fig. 4 where it is shown that a 1 minute RTA at 575 o C increased the PVCR of the devices to >2.6 along with a slight increase in the PCD. In this presentation, these results are compared to previous RITDs that did not demonstrate negative differential resistance when fabricated on as-grown substrates and explain the material properties behind the differences in performance. 978-1-4244-1892-3/07/$25.00 ©2007 IEEE Authorized licensed use limited to: Rochester Institute of Technology. Downloaded on April 06,2010 at 10:30:24 EDT from IEEE Xplore. Restrictions apply.