Thermal stability of sectorial split-drain magnetic field-effect transistors Wing-Shan Tam a,b,⇑ , Chi-Wah Kok a , Sik-Lam Siu c,d , Wing-Man Tang b , Chi-Wah Leung b , Hei Wong c a Canaan Semiconductor Ltd., Hong Kong b Department of Applied Physics, Hong Kong Polytechnic University, Hung Hum, Hong Kong c Department of Electronic Engineering, City University of Hong Kong, Kowloon Tong, Hong Kong d Department of Electrical and Electronic Engineering, University of Hong Kong, Pokfulam, Hong Kong article info Article history: Received 15 August 2013 Accepted 2 December 2013 Available online 6 January 2014 abstract The effect of charge trapping on the performance of sectorial Split-Drain Magnetic Field Effect Transistor (SD-MAGFET) under the influence of magnetic field is examined based on conventional capacitance mea- surement techniques upon different magnetic field strength and thermal conditions. The experimental results confirmed the charge trapping effect in sectorial SD-MAGFET is magnetic field and temperature dependent, where the charge trapping sites are localized at the channel boundary, which verifies the conjecture of trap-assisted magnetic sensitivity hysteresis and deterioration of the device found in recent literatures. The results of the study are useful to sectorial SD-MAGFET in high performance magnetic sensing applications. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Split-Drain Magnetic Field Effect Transistor (SD-MAGFET) man- ufactured with conventional CMOS compatible process has been a promising candidate to the magnetic sensor that can integrate with other circuits on a single chip [1,2]. The SD-MAGFET can be fabri- cated with different shapes (with respect to the channel), such as rectangular, sectorial, and circular, etc., where the sectorial SD- MAGFET is shown to be able to achieve the best magnetic sensitiv- ity with a given silicon size [3–5]. However, their applications have been limited by unknown sensitivity limitation and deterioration. Recent publications have shown that the sensitivity limitation and deterioration are geometric dependent [4,5], and they are caused by trapped charges [6]. The magnetic stressing study in Ref. [7] shows that the performance of the sectorial SD-MAGFET would be affected by charges trapped on the channel sidewall. However, there has been insufficient information to pinpoint the location of charge trapping that affects the operation of the secto- rial SD-MAGFET. It is the objective of this study to provide additional evidence on the location of charge trapping that affects the performance of the sectorial SD-MAGFET under the influence of an external magnetic field. We shall study the inference of charge trapping on sectorial SD-MAGFET through measuring the gate-to-drain capacitance (C gd ) of sectorial SD-MAGFET with a low voltage to bias the gate- to-drain interface under the influence of an external magnetic field. The C gd is studied because when the biasing voltage between gate- to-drain is low, the only possible location for charge trapping is the channel sidewall which is also known as the channel boundary. Therefore, our study will help to pinpoint where the charge trap- ping occurs in the sectorial SD-MAGFET under the influence of an external magnetic field. We shall further study the geometric dependence of the amount of charge trapping in sectorial SD-MAG- FET under the influence of external magnetic field. Our study shall conclude with a discussion on such geometric dependence and it’s implication on the application of sectorial SD-MAGFET as magnetic sensor in real world. 2. Channel boundary charge trapping Showing in Fig. 1 is the micrograph and layout of a sectorial SD- MAGFET that we shall study in this paper, where similar devices have been studied in [6,7]. The device under study is an N-channel sectorial SD-MAGFET which consists of a source terminal (Source) and two drain terminals (Drains 1 and 2). The darker gray color re- gion in the figure identifies the channel region, while the lighter gray color regions identify the source and drain regions. The arc of the overlap sector of the gate and drain terminals is the channel width W of the sectorial SD-MAGFET. The channel length, the radius of the source terminal, the spacing between the two drain terminals, the drain channel overlap, and the angle sustained by the sectorial SD-MAGFET are denoted as L; R; d; u and a, respec- tively. When a magnetic field B is applied perpendicular to the channel (as indicated by the cross in the figure), a Lorentz force will be induced that deflects the electrons in the channel from reaching Drain 2 to Drain 1, and thus creates a differential current known as the Hall current [2] given by DI H ¼ I DS1  I DS2 , where I DS1 and I DS2 are the drain currents measured at Drains 1 and 2, respectively. 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.12.006 ⇑ Corresponding author at: Canaan Semiconductor Limited, Fotan, Shatin, New Territories, Hong Kong. Tel.: +852 36196533. E-mail address: wstam@ieee.org (W.-S. Tam). Microelectronics Reliability 54 (2014) 1115–1118 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel