AN ENERGY EFFICIENT HALF-STATIC CLOCK-GATING D-TYPE FLIP-FLOP ¤ WING-SHAN TAM, OI-YING WONG, KA-YAN MOK, CHI-WAH KOK and HEI WONG * Department of Electronic Engineering, The City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong * heiwong@ieee.org Received 20 January 2008 Accepted 6 November 2009 This paper presents a new design of half-static clock-gating D-type °ip-°op (DFF). The pro- posed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock-gating circuitry. The new circuit has a very compact size, and can achieve low-power dissipation, especially in the case of low data activity. SPICE simulation results of the proposed DFF implemented with 0.18 m CMOS technology are presented, which shows that the overall performance of the present design is better than most of the DFFs reported in literatures. Keywords: D °ip-°op; half-static °ip-°op; °ip-°op. 1. Introduction Sequential circuits are often realized using D-type °ip-°ops (DFFs), which con- tribute the most signi¯cant portion of the total power dissipation of the digital circuits. Thus, DFFs with low-power dissipation are desirable in low-power designs. The power dissipation of sequential circuits is comprised of two sources, the static power dissipation and the dynamic power dissipation. The static power dissipation is indispensable for holding the circuit logic, and is mainly aroused from device lea- kages. This leakage current problem is not that severe in the technology with long channel length. With the device downscaling, the leakage current caused by the short channel e®ect cannot be neglected. There are di®erent methods to reduce or suppress the leakage current, mainly by controlling the process parameters or modifying the device structure, for examples, using high-k material as the MOSFET gate dielectric, or altering the substrate bias. Circuit techniques are also presented to alleviate the leakage current problem, for examples, reverse body bias or adaptive body bias. However, it results in complicated circuits or di±culties in layout. Note that the * This paper was recommended by Regional Editor Krishna Shenai. Journal of Circuits, Systems, and Computers Vol. 19, No. 3 (2010) 635654 # . c World Scienti¯c Publishing Company DOI: 10.1142/S0218126610006335 635