RADIOENGINEERING, VOL. 21, NO. 1, APRIL 2012 219 Sub-wavelength Lithography and Variability Aware SRAM Characterization Petr DOBROVOLNÝ, Miguel MIRANDA, Paul ZUBER Dept. of Design and Tech. Enablement, Div. of Process Technology, Imec vzw., Kapeldreef 75, B-3001 Leuven, Belgium dobrovol@imec.be, miranda@imec.be, zuberp@imec.be Abstract. With shrinking of minimum feature size of advanced technology nodes, the impact of litho process variations on the resulting electrical parameters of printed circuits dramatically increases. Litho process variations correspond to random changes in the actual optical conditions (dose and focus) which develop at every mask exposure, hence from die to die. In this way the litho process variations act as a global variability component affecting all devices on a particular die in the same way. In contrast to this, the intrinsic variability of the devices and interconnects originating mostly from local Random Dopant Fluctuations (RDF) and Line Edge Roughness (LER) has a purely spatially uncorrelated component. Yet, it is not clear which of the two limits scaling down variability sensitive circuits such as SRAM beyond 45 nm. This paper presents a tool flow to perform SRAM wide statistical analysis subject to combinations of global litho and local variability components. The tool flow is illustrated in 45 nm industry grade SRAM vehicle. Selected case studies show how this tool flow successfully captures non-trivial statistical interactions between the SRAM cell and the periphery, otherwise less visible when using statistical electrical simulations of the critical path alone. Keywords Litho process and technology variability, statistical SRAM analysis, yield prediction. 1. Introduction In this paper we present an approach offering full memory statistical analysis capabilities addressing litho and technology process variation effects and aiming at improving design productivity of embedded SRAM products. We show how the most likely reasons for statistical failure can be anticipated at design time so as to correct weak design spots before tape-out, hence avoiding costly silicon spin iterations. The technique provides key help to memory and system designers to estimate parametric and functional yield loss due to statistical parametric spreads in threshold voltage and/or current gain of the devices. Hence it is of especial value to the design of embedded SRAMs, which are considered to be the most sensitive SoC components to process variations. The estimated yield loss can be of parametric nature (i.e., failure of the memory access to meet the target cycle time or insufficient read margin for successful operation or similar); but it can be of functional nature (i.e., failure to meet a stability criteria or any other pass/fail functional check). The strength of the approach lies on successfully capturing all (non-trivial) memory-wide statistical inter- actions between the SRAM cell and the periphery, otherwise less visible when using statistical electrical simulations of the critical path alone. The tool flow requires five main input items. The first is a transistor level netlist description of a segment of the memory describing all circuitry involved from input to output. The second one is a memory layout designed according to prescribed design rules. The third one is information about litho process conditions. For the needs of litho variability analysis a process conditions region is represented by a set of pairs – dose/focus numbers – carefully selected from the border of a litho process windows. The fourth one is a set of parameters describing the internal architecture of the memory, thus how the memory is built from the segment information, including redundancy and error correction code infrastructure. The fifth one is information about the variability of the devices and interconnects used in the underlying technology. This information can be provided in either the form of statistical distributions of certain transistor parameters, scattered data obtained via statistical simulation of the device or just plain DC current-voltage statistical relationships of fabricated devices obtained during silicon characterization. The approach consists of two main phases. The first phase (see Fig. 1) performs litho variability analysis of a memory layout. Based on litho process analysis, the critical path netlist of a memory is updated, namely transistor sizes are adjusted. The degree of litho process impact on device size changes depends on a particular process conditions and on the layout itself, specifically on design rules applied for memory layout design. Thus the