Performance Debugging of Parallel and Distributed Embedded Systems F.J. Su´ arez, D.F. Garc´ ıa, J. Garc´ ıa Universidad de Oviedo Area de Arquitectura y Tecnolog´ ıa de Computadores Departamento de Informtica Campus de Viesques s/n, 33204 Gij´ on, Spain fran@atc.uniovi.es Abstract Validation, a crucial stage in the development cycle of embedded systems, is normally carried out using static analysis based on scheduling techniques. In high perfor- mance embedded systems, where several tasks with high computing requirements are working on input and output signals with high sampling rates, parallel and distributed processing is a valuable design alternative in order for the system to achieve the fulfillment of its real-time constraints. When the validation of parallel and distributed embedded systems is considered, many simplifications are made in or- der to make analysis tractable. This means that even if the system can be statically validated, the real behaviour of the system in execution may be different enough from its theo- retical behaviour to make it invalid. Thus, conservative de- signs that lead to over-dimensioned systems with partially wasted resources are commonly adopted. Although static analysis is the only alternative in case of critical embedded systems, where the fulfillment must be always guaranteed, dynamic analysis, based on measurement, is an interesting alternative for validation of non-critical embedded systems. This paper 1 describes a methodology for performance debugging of parallel and distributed embedded systems with non-critical end-to-end deadlines. The methodology is based on the measurement of a prototype of the system in execution and is supported by a behavioural model. The main components of the model are the sequences of activi- ties through out the system tasks (transactions), which are carried out in response to input events, causing the corre- sponding output events. Thus, the temporal behaviour of the system is viewed as a set of real-time transactions com- peting for the available resources. The paper also includes experimental results corresponding to the performance de- bugging of a well-known case study. 1 This research work has been supported by the ESPRIT HPC 8169 project ES- CORT. Keywords Embedded Systems; Parallel and Distributed Processing; Measurement; Performance Debugging Methodology; 1 Introduction Validation have been highlighted as a key area of re- search for real-time and embedded computing [20]. Static analysis, based on formal methods and scheduling theory; and dynamic analysis, based on simulation and run-time measurement, are the two approaches most commonly used for timing analysis and validation. In high performance embedded systems, commonly im- plemented as parallel or distributed systems, timing con- straints must be derived and imposed based on the end- to-end requirements between input events (usually from the external environment of the system), and output events (generated by the system in response to the input events). This end-to-end approach has been followed by several au- thors in the real-time computing area, working with mono- processor systems [4], parallel systems [22] and distributed systems [8, 16]. As a result, the system can be modeled as a set of communicating end-to-end tasks. Real-time scheduling, the most common approach in re- lated literature, produces low degrees of success with sys- tems whose end-to-end tasks may have complex synchro- nization patterns (i.e. not only pipeline patterns, but fork- join patterns as well) and widely varying releases, execu- tion times and resource requirements. The problem with scheduling theory for this kind of systems comes from the fact that the models we use incorporate many simplifica- tions in order to make the problem tractable. Thus, a sys- tem which is perfectly schedulable in theory, may not be schedulable in practice, after implementation on a specific platform. This is why these kinds of embedded systems must be over-dimensioned so that the real-time constraints are always fulfilled. Here, trade-offs between dependability and minimum waste of resources become a key point in the design of the embedded system.