International Journal of Science Technology & Management www.ijstm.com Volume No.04, Special Issue No.01, February 2015 ISSN (Print) 2394-1529, (Online) 2394-1537 63 | Page A NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY Ms. Chaitali V. Matey 1 , Ms. Shraddha K. Mendhe 2 , Mr. Sandip A. Zade 3 1,2,3 Electronics and Comm. Dept, Suresh Deshmukh College of Engg. Wardha (MS), (India) ABSTRACT The design of high-performance and low-power clocked storage elements is essential and critical to achieving maximum levels of performance and reliability in modern VLSI systems such as Systems o Chips (SoCs). TSPC D flip flop offers advantages in terms of speed and power over normal D Flip Flop design. As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance is implemented in layout level which develops the low power consumption chip, using recent CMOS, micron layout tools. This paper compares 2 architecture of 3 bit counter using normal Flip flop design and TSPC D flip flop design in terms of speed, power consumption and CMOS layout using 45 nm CMOS technology. Micro wind CMOS layout design tool allows the designer to design and simulate an integrated circuit at physical description level. Index Terms: Microwind, Micron Technology, Layout, Asynchronous Counter. I. INTRODUCTION Counters are sequential circuits that keep tract of the number of pulses applied on their inputs. They occur frequently in real-world, practical digital systems, with applications in computer systems, communication equipments, scientific instruments, and industrial control, to name a few. Many counter designs have been proposed in literature, patents, and/or used in practice. Counters are usually classified into synchronous counters, such as ring counters and twisted counters, and asynchronous counters, such as ripple counter. In CPUs, microcontrollers, DSPs and many other digital designs which include a program counter, and a timer counter, synchronous counters are usually preferred. Counters are often clocked at a very high rate, usually with an activity factor of 1. In a good design however, the activity factor can be substantially less than 1 and data- dependent leading to lower power consumption. A counter is a logic circuit that counts the number of occurrence of an input. Each count, a binary number is