A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems Hamid Fadishei, Mehdi Saeedi * , Morteza Saheb Zamani VLSI CAD Lab, Computer Engineering Department, Amirkabir University of Technology, Tehran, Iran Available online 20 February 2008 Abstract With today’s networks complexity, routers in backbone links must be able to handle millions of packets per second on each of their ports. Determining the corresponding output interface for each incoming packet based on its destination address requires a longest matching prefix search on the IP address. Therefore, IP address lookup is one of the most challenging problems for backbone routers. In this paper, an IP routing lookup architecture is proposed which is based on a reconfigurable hardware platform. Experimental results show that the rate of 193 million lookups per second is achieved using our architecture while prefixes can be updated with a rate of 3 million updates per second. Furthermore, it was shown that using our reconfigurable architecture results in rare update failure rate due to resource limitations. Ó 2008 Elsevier B.V. All rights reserved. Keywords: IP address lookup; Longest prefix matching (LPM); Reconfigurable hardware; Hashing; Field-programmable gate array (FPGA) 1. Introduction The advents of the World Wide Web (WWW) and band- width-hungry applications such as video-on-demand and distance learning have resulted in the growth of traffic rates on backbone links. Such new applications together with the increase in the number of Internet users add new challenges to the design of today’s multi-gigabit IP networks. Although, the link speed and router throughput have been improved by optical data transmission links and new data switching technologies, the packet forwarding rate is still a challenging problem [1]. Therefore, deployment of high performance packet forwarding routers is a key issue for designing multi-gigabit networks. On the other hand, to design a multi-gigabit packet forwarding router, many problems should be resolved. IP address lookup, checking packet checksum for errors, updating the checksum and decreasing packet time-to-live (TTL) are common responsi- bilities of routers. However, the IP address lookup is par- ticularly one of the most challenging ones. With the aim of using IP address space more efficiently and to slow down the growth of forwarding tables in back- bone routers, classless inter-domain routing (CIDR) scheme was introduced [2]. While CIDR reduces the size of forwarding tables, the address lookup problem has now become more complex. With CIDR, each IP route is identified by a route prefix and a prefix length which is var- iable between 0 and 32. When a packet is received, the rou- ter looks up in its forwarding table for the longest match with the packet destination’s IP address. As a result, deter- mining the longest matching prefix involves not only com- paring the bit pattern itself, but also finding the appropriate length. Hence, the well-known schemes for exact matching, such as perfect matching and standard content addressable memories (CAMs), cannot be directly employed for IP route lookups [3] and this makes the lookup operation more difficult. To have an efficient IP address lookup architecture, dif- ferent objectives should be considered [4]. First, lookup operations must be done fast. Consider IP packets which 0141-9331/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.micpro.2008.01.001 * Corresponding author. Tel.: +98 21 64542734; fax: +98 21 6495521. E-mail address: msaeedi@aut.ac.ir (M. Saeedi). www.elsevier.com/locate/micpro Available online at www.sciencedirect.com Microprocessors and Microsystems 32 (2008) 223–233