The International Journal of Microcircuits and Electronic Packaging, Volume 22, Number 4, Fourth Quarter 1999 (ISSN 1063-1674) © International Microelectronics And Packaging Society MCM-D/C Yield Improvements Through Effective Diagnostics 411 MCM-D/C Yield Improvements Through Effective Diagnostics Eric D. Perfecto, Kamalesh S. Desai, and Graham McAfee IBM Microelectronics 1580 Route 52, MS20A Hopewell Junction, New York 12533 Phone: 914-894-4400 Fax: 914-892-6208 e-mail: perfecto@us.ibm.com Abstract Partitioning of defects in process, tools, contamination, and handling has been used effectively at IBM Thin Films Packaging manu- facturing facility for many years to track and improve yields. On multilevel structures, final test alone does not allow for effective diagnostic since most yield losses occur from sub-level defects. Early feedback to establish root cause can be obtained via in-line test, inspection, and measurement. Also, it is at these sub-levels where surface repairs for opens and shorts can be easily achieved. Yield improvements are achieved by establishing an effective diagnostic process. This process consists of data mining, focus inspection, process-steps partitioning, and failure analysis working together to establish the defect root cause by recreation experiments, fol- lowed by verification of corrective actions on send ahead parts. Specific examples will illustrate how scattered plots, failure analysis, job traceability, and correlations have been used at IBM MCM-D/C manufacturing line for real time defect diagnosis. For new products start, the designer must work with the development and manufacturing team so that adequate consideration is given to design-for-manufacturability (DFM) elements such as tool, clean room environment, process selection, ground rules, repairability, test, and cost. Key words: MCM-D, MCM-D/C, Manufacturing, Defect Partitioning, Yield, and Diagnostics. 1. Introduction Thin film processes for packaging resemble those of semi- conductor personalization processes practiced over fifteen years, in terms of their required ground rules. Packaging processes utilize subtractive etching and more recently, pattern electroplat- ing for wiring definition, and laser ablation, photosensitive polyimide (PSPI), wet and reactive ion etching (RIE) for organic dielectric via definition 1,2 . However, packaging differs from semi- conductor in two ways: 1) It requires large area processing, par- ticularly, for multichip module (MCM-D) applications, and 2) Its long transmission lines necessitate the use of thicker conduc- tion lines 3 . Additionally, thicker dielectric, typically polyimide, is required to satisfy 50 ohms matching impedance package. There are many challenges when thin films are fabricated serially on top of an active ceramic or Aluminum Nitride (AlN) substrate (MCM-D/C): 1) One plane pair structures containing a minimum of two mesh and two wiring levels result in long cycle times. 2) Special dielectric and resist apply tooling is re- quired for handling thick, heavy, and square ceramic substrates, since semiconductor tools are designed for thin coatings on light wafers. 3) Cofired MCM-C substrates have via pattern distor- tion, camber, and surface defects which require mapping and surface preparations, such as planarization and polishing 4 . 4) Precautions must be taken to ensure no chemical interactions